DE69229424D1 - Adressengeneration in einer Datenverarbeitungseinheit - Google Patents
Adressengeneration in einer DatenverarbeitungseinheitInfo
- Publication number
- DE69229424D1 DE69229424D1 DE69229424T DE69229424T DE69229424D1 DE 69229424 D1 DE69229424 D1 DE 69229424D1 DE 69229424 T DE69229424 T DE 69229424T DE 69229424 T DE69229424 T DE 69229424T DE 69229424 D1 DE69229424 D1 DE 69229424D1
- Authority
- DE
- Germany
- Prior art keywords
- addresses
- generation
- processing unit
- data processing
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/342—Extension of operand address space
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30112—Register structure comprising data of variable length
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP09584391A JP3181307B2 (ja) | 1991-04-25 | 1991-04-25 | 命令処理装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69229424D1 true DE69229424D1 (de) | 1999-07-22 |
DE69229424T2 DE69229424T2 (de) | 1999-11-18 |
Family
ID=14148658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69229424T Expired - Fee Related DE69229424T2 (de) | 1991-04-25 | 1992-04-23 | Adressengeneration in einer Datenverarbeitungseinheit |
Country Status (5)
Country | Link |
---|---|
US (1) | US5835973A (de) |
EP (1) | EP0510635B1 (de) |
JP (1) | JP3181307B2 (de) |
KR (1) | KR960008318B1 (de) |
DE (1) | DE69229424T2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5915266A (en) * | 1994-05-25 | 1999-06-22 | National Semiconductor Corporation | Processor core which provides a linear extension of an addressable memory space |
US5566308A (en) * | 1994-05-25 | 1996-10-15 | National Semiconductor Corporation | Processor core which provides a linear extension of an addressable memory space |
WO1995032467A1 (en) * | 1994-05-25 | 1995-11-30 | National Semiconductor Corporation | Processor core which provides a linear extension of an addressable memory space |
US5819056A (en) * | 1995-10-06 | 1998-10-06 | Advanced Micro Devices, Inc. | Instruction buffer organization method and system |
US5809327A (en) * | 1997-03-27 | 1998-09-15 | Atmel Corporation | Eight-bit microcontroller having a risc architecture |
US5940877A (en) * | 1997-06-12 | 1999-08-17 | International Business Machines Corporation | Cache address generation with and without carry-in |
US6098160A (en) * | 1997-10-28 | 2000-08-01 | Microchip Technology Incorporated | Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor |
US7254696B2 (en) * | 2002-12-12 | 2007-08-07 | Alacritech, Inc. | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests |
US7334116B2 (en) * | 2004-10-06 | 2008-02-19 | Sony Computer Entertainment Inc. | Bit manipulation on data in a bitstream that is stored in a memory having an address boundary length |
CN100351813C (zh) * | 2005-09-07 | 2007-11-28 | 大唐微电子技术有限公司 | 数字信号处理系统中访问存储单元的方法及其处理系统 |
KR102552666B1 (ko) * | 2018-11-12 | 2023-07-10 | 삼성전자주식회사 | 전자 장치 및 그것의 동작 방법 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3657705A (en) * | 1969-11-12 | 1972-04-18 | Honeywell Inc | Instruction translation control with extended address prefix decoding |
US3976976A (en) * | 1975-04-04 | 1976-08-24 | The United States Of America As Represented By The Secretary Of The Navy | Method and means to access and extended memory unit |
US4090237A (en) * | 1976-09-03 | 1978-05-16 | Bell Telephone Laboratories, Incorporated | Processor circuit |
US4206503A (en) * | 1978-01-10 | 1980-06-03 | Honeywell Information Systems Inc. | Multiple length address formation in a microprogrammed data processing system |
US4363091A (en) * | 1978-01-31 | 1982-12-07 | Intel Corporation | Extended address, single and multiple bit microprocessor |
JPS6017130B2 (ja) * | 1980-06-06 | 1985-05-01 | 日本電気株式会社 | アドレス制御装置 |
IT1183808B (it) * | 1985-04-30 | 1987-10-22 | Olivetti & Co Spa | Circuito elettronico per collegare un microprocessore ad una memoria ad elevata capacita |
US4868740A (en) * | 1986-06-04 | 1989-09-19 | Hitachi, Ltd. | System for processing data with multiple virtual address and data word lengths |
JPH0192851A (ja) * | 1987-10-02 | 1989-04-12 | Hitachi Ltd | アドレス空間切替装置 |
-
1991
- 1991-04-25 JP JP09584391A patent/JP3181307B2/ja not_active Expired - Fee Related
-
1992
- 1992-04-16 KR KR1019920006348A patent/KR960008318B1/ko not_active IP Right Cessation
- 1992-04-23 DE DE69229424T patent/DE69229424T2/de not_active Expired - Fee Related
- 1992-04-23 EP EP92106940A patent/EP0510635B1/de not_active Expired - Lifetime
-
1996
- 1996-08-14 US US08/696,103 patent/US5835973A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR920020322A (ko) | 1992-11-21 |
DE69229424T2 (de) | 1999-11-18 |
JP3181307B2 (ja) | 2001-07-03 |
EP0510635A3 (en) | 1993-07-07 |
EP0510635B1 (de) | 1999-06-16 |
US5835973A (en) | 1998-11-10 |
EP0510635A2 (de) | 1992-10-28 |
JPH04363735A (ja) | 1992-12-16 |
KR960008318B1 (ko) | 1996-06-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |