DE69229093D1 - Verfahren zur Prüfsequenzerzeugung - Google Patents

Verfahren zur Prüfsequenzerzeugung

Info

Publication number
DE69229093D1
DE69229093D1 DE69229093T DE69229093T DE69229093D1 DE 69229093 D1 DE69229093 D1 DE 69229093D1 DE 69229093 T DE69229093 T DE 69229093T DE 69229093 T DE69229093 T DE 69229093T DE 69229093 D1 DE69229093 D1 DE 69229093D1
Authority
DE
Germany
Prior art keywords
state
fault
circuit
test sequence
illegal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229093T
Other languages
English (en)
Other versions
DE69229093T2 (de
Inventor
Toshinori Hosokawa
Akira Motohara
Mitsuyasu Ohta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69229093D1 publication Critical patent/DE69229093D1/de
Publication of DE69229093T2 publication Critical patent/DE69229093T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69229093T 1991-09-30 1992-09-28 Verfahren zur Prüfsequenzerzeugung Expired - Fee Related DE69229093T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3250883A JPH0587885A (ja) 1991-09-30 1991-09-30 検査系列生成方法

Publications (2)

Publication Number Publication Date
DE69229093D1 true DE69229093D1 (de) 1999-06-10
DE69229093T2 DE69229093T2 (de) 1999-11-25

Family

ID=17214439

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229093T Expired - Fee Related DE69229093T2 (de) 1991-09-30 1992-09-28 Verfahren zur Prüfsequenzerzeugung

Country Status (4)

Country Link
US (1) US5483543A (de)
EP (1) EP0535573B1 (de)
JP (1) JPH0587885A (de)
DE (1) DE69229093T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69333806T2 (de) * 1992-03-27 2005-10-06 Matsushita Electric Industrial Co., Ltd., Kadoma Verfahren und Gerät zur Prüfsequenzgenerierung
US6141630A (en) * 1997-08-07 2000-10-31 Verisity Design, Inc. System and method for automated design verification
TW564317B (en) * 1999-04-28 2003-12-01 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and the checking method
US6412085B1 (en) * 1999-08-13 2002-06-25 Intrinsity, Inc. Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state
US7073106B2 (en) * 2003-03-19 2006-07-04 International Business Machines Corporation Test method for guaranteeing full stuck-at-fault coverage of a memory array
US20070260926A1 (en) * 2006-04-13 2007-11-08 International Business Machines Corporation Static and dynamic learning test generation method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5257268A (en) * 1988-04-15 1993-10-26 At&T Bell Laboratories Cost-function directed search method for generating tests for sequential logic circuits
JPH04148882A (ja) * 1990-10-12 1992-05-21 Hitachi Ltd 論理集積回路の故障位置指摘方法

Also Published As

Publication number Publication date
JPH0587885A (ja) 1993-04-06
DE69229093T2 (de) 1999-11-25
EP0535573A3 (en) 1996-08-07
EP0535573A2 (de) 1993-04-07
EP0535573B1 (de) 1999-05-06
US5483543A (en) 1996-01-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee