DE69226254T2 - Verbesserungen in digitalen Kommunikationssystemen oder in bezug auf digitale Kommunikationssysteme - Google Patents

Verbesserungen in digitalen Kommunikationssystemen oder in bezug auf digitale Kommunikationssysteme

Info

Publication number
DE69226254T2
DE69226254T2 DE69226254T DE69226254T DE69226254T2 DE 69226254 T2 DE69226254 T2 DE 69226254T2 DE 69226254 T DE69226254 T DE 69226254T DE 69226254 T DE69226254 T DE 69226254T DE 69226254 T2 DE69226254 T2 DE 69226254T2
Authority
DE
Germany
Prior art keywords
signal
clock
synchronisation
received data
approximate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69226254T
Other languages
English (en)
Other versions
DE69226254D1 (de
Inventor
Antony J Wray
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions UK Ltd
Original Assignee
Motorola Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Ltd filed Critical Motorola Ltd
Application granted granted Critical
Publication of DE69226254D1 publication Critical patent/DE69226254D1/de
Publication of DE69226254T2 publication Critical patent/DE69226254T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Multicomponent Fibers (AREA)
DE69226254T 1991-08-15 1992-08-13 Verbesserungen in digitalen Kommunikationssystemen oder in bezug auf digitale Kommunikationssysteme Expired - Fee Related DE69226254T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB919117645A GB9117645D0 (en) 1991-08-15 1991-08-15 Improvements in or relating to digital communication systems
PCT/EP1992/001853 WO1993004544A1 (en) 1991-08-15 1992-08-13 Improvements in or relating to digital communication systems

Publications (2)

Publication Number Publication Date
DE69226254D1 DE69226254D1 (de) 1998-08-20
DE69226254T2 true DE69226254T2 (de) 1999-03-04

Family

ID=10700039

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69226254T Expired - Fee Related DE69226254T2 (de) 1991-08-15 1992-08-13 Verbesserungen in digitalen Kommunikationssystemen oder in bezug auf digitale Kommunikationssysteme

Country Status (8)

Country Link
US (1) US5446766A (de)
EP (1) EP0553324B1 (de)
JP (1) JP2917522B2 (de)
AT (1) ATE168511T1 (de)
DE (1) DE69226254T2 (de)
ES (1) ES2118138T3 (de)
GB (1) GB9117645D0 (de)
WO (1) WO1993004544A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0177733B1 (ko) * 1994-08-26 1999-05-15 정장호 데이타 전송장치의 클럭동기 회로
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
US5646564A (en) * 1994-09-02 1997-07-08 Xilinx, Inc. Phase-locked delay loop for clock correction
US5805871A (en) * 1995-07-21 1998-09-08 Ricoh Company Ltd. System and method for phase-synchronous, flexible-frequency clocking and messaging
US5920600A (en) * 1995-09-18 1999-07-06 Oki Electric Industry Co., Ltd. Bit phase synchronizing circuitry for controlling phase and frequency, and PLL circuit therefor
CN1086521C (zh) * 1997-04-25 2002-06-19 松下电器产业株式会社 减小时钟信号和数据信号间失真的集成电路、系统和方法
NO307728B1 (no) * 1997-06-03 2000-05-15 Abb Research Ltd Fremgangsmåte for å skaffe tidssynkronisering i et nettverk
US7639054B1 (en) * 2008-01-16 2009-12-29 Altera Corporation Techniques for generating programmable delays
KR20160078423A (ko) * 2013-12-28 2016-07-04 인텔 코포레이션 에뮬레이션 및 프로토타이핑 플랫폼 상의 파티셔닝에 의한 동적 상호접속부

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2945331C2 (de) * 1979-11-09 1984-05-30 Nixdorf Computer Ag, 4790 Paderborn Vorrichtung in einer Signal-oder Datenverarbeitungsanlage zur Einstellung einer Signalverarbeitungsschaltung
US4630267A (en) * 1983-12-23 1986-12-16 International Business Machines Corporation Programmable timing and synchronization circuit for a TDMA communications controller
DE3431419C1 (de) * 1984-08-27 1986-02-13 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Schaltungsanordnung zum Synchronisieren des empfangsseitig erzeugten Taktsignals mit bei digitaler Informationsuebertragung empfangenen Taktsignale in Fernmeldeanlagen
US4795985A (en) * 1986-04-01 1989-01-03 Hewlett-Packard Company Digital phase lock loop
JPH02256329A (ja) * 1988-12-01 1990-10-17 Nec Corp 復調器制御方式

Also Published As

Publication number Publication date
JPH06507769A (ja) 1994-09-01
EP0553324B1 (de) 1998-07-15
US5446766A (en) 1995-08-29
GB9117645D0 (en) 1991-10-02
DE69226254D1 (de) 1998-08-20
EP0553324A1 (de) 1993-08-04
ES2118138T3 (es) 1998-09-16
JP2917522B2 (ja) 1999-07-12
ATE168511T1 (de) 1998-08-15
WO1993004544A1 (en) 1993-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee