DE69129566D1 - Hochgeschwindigkeitsbussystem - Google Patents

Hochgeschwindigkeitsbussystem

Info

Publication number
DE69129566D1
DE69129566D1 DE69129566T DE69129566T DE69129566D1 DE 69129566 D1 DE69129566 D1 DE 69129566D1 DE 69129566 T DE69129566 T DE 69129566T DE 69129566 T DE69129566 T DE 69129566T DE 69129566 D1 DE69129566 D1 DE 69129566D1
Authority
DE
Germany
Prior art keywords
high speed
bus system
speed bus
speed
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69129566T
Other languages
English (en)
Other versions
DE69129566T2 (de
Inventor
Ray Ramanujan
James B Keller
William A Samaras
John Derosa
Robert E Stewart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE69129566D1 publication Critical patent/DE69129566D1/de
Application granted granted Critical
Publication of DE69129566T2 publication Critical patent/DE69129566T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
DE1991629566 1990-06-29 1991-06-28 Hochgeschwindigkeitsbussystem Expired - Fee Related DE69129566T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US54654790A 1990-06-29 1990-06-29

Publications (2)

Publication Number Publication Date
DE69129566D1 true DE69129566D1 (de) 1998-07-16
DE69129566T2 DE69129566T2 (de) 1998-12-17

Family

ID=24180912

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1991629566 Expired - Fee Related DE69129566T2 (de) 1990-06-29 1991-06-28 Hochgeschwindigkeitsbussystem

Country Status (5)

Country Link
EP (1) EP0464708B1 (de)
JP (1) JPH04280347A (de)
AU (1) AU636739B2 (de)
CA (1) CA2042711A1 (de)
DE (1) DE69129566T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2285524B (en) * 1994-01-11 1998-02-04 Advanced Risc Mach Ltd Data memory and processor bus
US5754865A (en) * 1995-12-18 1998-05-19 International Business Machines Corporation Logical address bus architecture for multiple processor systems
FR2759472B1 (fr) * 1997-02-12 1999-05-07 Thomson Csf Registre semaphore rapide a fonctionnement securise sans protocole de bus specifique
US6732255B1 (en) * 1999-09-15 2004-05-04 Koninklijke Philips Electronics N.V. Can microcontroller that permits concurrent access to different segments of a common memory by both the processor core and the DMA engine thereof
JP4198376B2 (ja) * 2002-04-02 2008-12-17 Ｎｅｃエレクトロニクス株式会社 バスシステム及びバスシステムを含む情報処理システム
KR100464036B1 (ko) * 2002-09-07 2005-01-03 엘지전자 주식회사 멀티프로세서의 정보 교환 장치
JP4249741B2 (ja) * 2005-11-04 2009-04-08 Ｎｅｃエレクトロニクス株式会社 バスシステム及びバスシステムを含む情報処理システム
CN114036091B (zh) * 2021-10-30 2023-06-16 西南电子技术研究所（中国电子科技集团公司第十研究所） 多处理器外设复用电路及其复用方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3340123A1 (de) * 1983-11-05 1985-05-15 Helmut Dipl.-Inform. 5860 Iserlohn Bähring Kommunikationseinheit zur kopplung von mikrorechnern
EP0257061A1 (de) * 1986-02-10 1988-03-02 EASTMAN KODAK COMPANY (a New Jersey corporation) Vielfachprozessorvorrichtung
JPH02115962A (ja) * 1988-10-26 1990-04-27 K S D:Kk コンピュータ装置とその周辺装置との接続方式

Also Published As

Publication number Publication date
EP0464708A1 (de) 1992-01-08
CA2042711A1 (en) 1991-12-30
AU636739B2 (en) 1993-05-06
JPH04280347A (ja) 1992-10-06
EP0464708B1 (de) 1998-06-10
DE69129566T2 (de) 1998-12-17
AU7528191A (en) 1992-03-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee