DE69127772D1 - Master-/Slave-Prüfsystem - Google Patents

Master-/Slave-Prüfsystem

Info

Publication number
DE69127772D1
DE69127772D1 DE69127772T DE69127772T DE69127772D1 DE 69127772 D1 DE69127772 D1 DE 69127772D1 DE 69127772 T DE69127772 T DE 69127772T DE 69127772 T DE69127772 T DE 69127772T DE 69127772 D1 DE69127772 D1 DE 69127772D1
Authority
DE
Germany
Prior art keywords
master
outputs
mimicked
slave
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69127772T
Other languages
English (en)
Inventor
Brett B Stewart
David B Witt
Bo A Molander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69127772D1 publication Critical patent/DE69127772D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1637—Error detection by comparing the output of redundant processing systems using additional compare functionality in one or some but not all of the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Eye Examination Apparatus (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Telephone Function (AREA)
  • Selective Calling Equipment (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69127772T 1990-06-12 1991-06-03 Master-/Slave-Prüfsystem Expired - Lifetime DE69127772D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/536,884 US5157780A (en) 1990-06-12 1990-06-12 Master-slave checking system

Publications (1)

Publication Number Publication Date
DE69127772D1 true DE69127772D1 (de) 1997-11-06

Family

ID=24140324

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127772T Expired - Lifetime DE69127772D1 (de) 1990-06-12 1991-06-03 Master-/Slave-Prüfsystem

Country Status (5)

Country Link
US (1) US5157780A (de)
EP (1) EP0461792B1 (de)
JP (1) JPH0683658A (de)
AT (1) ATE158880T1 (de)
DE (1) DE69127772D1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5754757A (en) * 1992-11-06 1998-05-19 The University Of Newcastle Upon Tyne Efficient schemes for constructing reliable computing nodes in distributed systems
US5758058A (en) * 1993-03-31 1998-05-26 Intel Corporation Apparatus and method for initializing a master/checker fault detecting microprocessor
US5574928A (en) * 1993-10-29 1996-11-12 Advanced Micro Devices, Inc. Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments
EP0651321B1 (de) * 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5632023A (en) * 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus
JP3611894B2 (ja) * 1995-03-30 2005-01-19 富士通株式会社 二重化構成をもつシステム制御装置
US5758063A (en) * 1995-05-04 1998-05-26 Micron Technology, Inc. Testing mapped signal sources
JP3991384B2 (ja) * 1996-07-15 2007-10-17 株式会社デンソー 電子制御装置
US5892897A (en) * 1997-02-05 1999-04-06 Motorola, Inc. Method and apparatus for microprocessor debugging
US6769073B1 (en) * 1999-04-06 2004-07-27 Benjamin V. Shapiro Method and apparatus for building an operating environment capable of degree of software fault tolerance
US6654909B1 (en) * 2000-06-30 2003-11-25 Intel Corporation Apparatus and method for protecting critical resources against soft errors in high performance microprocessors
EP1396771B1 (de) * 2001-05-31 2016-02-17 Omron Corporation Slave-einheiten und netzwerksystem, sowie slaveverarbeitungsverfahren und informationssammelverfahren
US7430451B2 (en) * 2001-05-31 2008-09-30 Omron Corporation Safety unit, controller system, connection method of controllers, control method of the controller system and monitor method of the controller system
US7472106B2 (en) * 2001-06-22 2008-12-30 Omron Corporation Safety network system and safety slave
US7003691B2 (en) * 2002-06-28 2006-02-21 Hewlett-Packard Development Company, L.P. Method and apparatus for seeding differences in lock-stepped processors
WO2004023312A1 (en) * 2002-08-05 2004-03-18 Infineon Technolgies Ag Methods for operating a cpu having an internal data cache
DE10325263B4 (de) * 2003-06-03 2013-09-19 Phoenix Contact Gmbh & Co. Kg Sicherstellung von maximalen Reaktionszeiten in komplexen oder verteilten sicheren und/oder nicht sicheren Systemen
US20040230867A1 (en) * 2003-05-15 2004-11-18 Ramin Soheili Method and system of using high-level code for independent debugging of a processor
DE502004012374D1 (de) * 2003-06-30 2011-05-19 Siemens Ag Verfahren zur überwachung des programmlaufs in einem mikro-computer
US7287184B2 (en) * 2003-09-16 2007-10-23 Rockwell Automation Technologies, Inc. High speed synchronization in dual-processor safety controller
US7526676B2 (en) * 2004-09-03 2009-04-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Slave device having independent error recovery
JP4900891B2 (ja) 2005-04-27 2012-03-21 キヤノン株式会社 通信装置及び通信方法
DE102007029116A1 (de) * 2007-06-25 2009-01-02 Continental Automotive Gmbh Verfahren zum Betreiben eines Mikrocontrollers und einer Ausführungseinheit sowie ein Mikrocontroller und eine Ausführungseinheit
US8243614B2 (en) * 2008-03-07 2012-08-14 Honeywell International Inc. Hardware efficient monitoring of input/output signals
TWI409665B (zh) * 2008-10-23 2013-09-21 Shrisinha Technology Corp Enter the information instantly against the protection method and its hardware
US8069367B2 (en) * 2009-05-05 2011-11-29 Lockheed Martin Corporation Virtual lock stepping in a vital processing environment for safety assurance
EP2447844B1 (de) * 2010-10-26 2022-09-14 Bombardier Transportation GmbH Prüfung des korrekten HMI-Betriebs
US8996953B2 (en) 2013-03-01 2015-03-31 International Business Machines Corporation Self monitoring and self repairing ECC

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1952349B2 (de) * 1969-10-17 1973-06-20 Anordnung zur pruefung eines redundanten regelsystems
US4358823A (en) * 1977-03-25 1982-11-09 Trw, Inc. Double redundant processor
JPS58109944A (ja) * 1981-12-23 1983-06-30 Kyosan Electric Mfg Co Ltd 不一致検出回路の故障検知方法
US4574343A (en) * 1982-09-29 1986-03-04 Kabushiki Kaisha Komatsu Seisakusho Contactless press control device
US4759019A (en) * 1986-07-10 1988-07-19 International Business Machines Corporation Programmable fault injection tool
US4792955A (en) * 1986-08-21 1988-12-20 Intel Corporation Apparatus for on-line checking and reconfiguration of integrated circuit chips
IT1213344B (it) * 1986-09-17 1989-12-20 Honoywell Information Systems Architettura di calcolatore a tolleranza di guasto.
JPH0792764B2 (ja) * 1988-05-25 1995-10-09 日本電気株式会社 マイクロプロセッサ
US4903270A (en) * 1988-06-14 1990-02-20 Intel Corporation Apparatus for self checking of functional redundancy check (FRC) logic
JPH0721769B2 (ja) * 1988-08-12 1995-03-08 日本電気株式会社 マイクロプロセッサの冗長構成による機能監視方式

Also Published As

Publication number Publication date
US5157780A (en) 1992-10-20
EP0461792A2 (de) 1991-12-18
ATE158880T1 (de) 1997-10-15
JPH0683658A (ja) 1994-03-25
EP0461792B1 (de) 1997-10-01
EP0461792A3 (en) 1993-01-13

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Legal Events

Date Code Title Description
8332 No legal effect for de