DE69127333D1 - Phasensynchronisiertes Oszillatorsystem mit Ma nahmen gegen Unterbrechung des Eingangstakts - Google Patents

Phasensynchronisiertes Oszillatorsystem mit Ma nahmen gegen Unterbrechung des Eingangstakts

Info

Publication number
DE69127333D1
DE69127333D1 DE69127333T DE69127333T DE69127333D1 DE 69127333 D1 DE69127333 D1 DE 69127333D1 DE 69127333 T DE69127333 T DE 69127333T DE 69127333 T DE69127333 T DE 69127333T DE 69127333 D1 DE69127333 D1 DE 69127333D1
Authority
DE
Germany
Prior art keywords
took
phase
input clock
locked oscillator
oscillator system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69127333T
Other languages
English (en)
Other versions
DE69127333T2 (de
Inventor
Hironao Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69127333D1 publication Critical patent/DE69127333D1/de
Application granted granted Critical
Publication of DE69127333T2 publication Critical patent/DE69127333T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H03L7/145—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop the switched reference signal being derived from the controlled oscillator output signal
DE69127333T 1990-10-02 1991-10-01 Phasensynchronisiertes Oszillatorsystem mit Ma nahmen gegen Unterbrechung des Eingangstakts Expired - Lifetime DE69127333T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26309390 1990-10-02

Publications (2)

Publication Number Publication Date
DE69127333D1 true DE69127333D1 (de) 1997-09-25
DE69127333T2 DE69127333T2 (de) 1998-01-02

Family

ID=17384735

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127333T Expired - Lifetime DE69127333T2 (de) 1990-10-02 1991-10-01 Phasensynchronisiertes Oszillatorsystem mit Ma nahmen gegen Unterbrechung des Eingangstakts

Country Status (3)

Country Link
US (1) US5164684A (de)
EP (1) EP0479237B1 (de)
DE (1) DE69127333T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06197014A (ja) * 1992-12-25 1994-07-15 Mitsubishi Electric Corp 位相同期回路
JP2518148B2 (ja) * 1993-03-12 1996-07-24 日本電気株式会社 クロック従属同期方法
CA2130871C (en) * 1993-11-05 1999-09-28 John M. Alder Method and apparatus for a phase-locked loop circuit with holdover mode
IT1278538B1 (it) * 1995-12-20 1997-11-24 Sits Soc It Telecom Siemens Procedimento per il mantenimento dell'aggancio in un pll digitale durante eventuali interruzioni transitorie del segnale sincronizzante
JP2000174616A (ja) * 1998-12-04 2000-06-23 Fujitsu Ltd 半導体集積回路
JP3179429B2 (ja) * 1999-01-29 2001-06-25 日本電気アイシーマイコンシステム株式会社 周波数測定用テスト回路及びそれを備えた半導体集積回路
US6522204B1 (en) 2000-11-28 2003-02-18 Texas Instruments Incorporated Phase-locked loop for ADSL frequency locking applications
JP4076391B2 (ja) 2002-07-30 2008-04-16 山洋電気株式会社 周期性信号制御装置及び周波数検出装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3882412A (en) * 1974-03-29 1975-05-06 North Electric Co Drift compensated phase lock loop
US4135166A (en) * 1978-04-26 1979-01-16 Gte Sylvania Incorporated Master timing generator
DE3302700A1 (de) * 1983-01-27 1984-08-02 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum einstellen der mittenfrequenz des oszillators eines phasenregelkreises
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator

Also Published As

Publication number Publication date
EP0479237A1 (de) 1992-04-08
US5164684A (en) 1992-11-17
EP0479237B1 (de) 1997-08-20
DE69127333T2 (de) 1998-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition