DE69125874D1 - Generator für mehrdimensionale Adressen und Anordnung zum Steuern desselben - Google Patents

Generator für mehrdimensionale Adressen und Anordnung zum Steuern desselben

Info

Publication number
DE69125874D1
DE69125874D1 DE69125874T DE69125874T DE69125874D1 DE 69125874 D1 DE69125874 D1 DE 69125874D1 DE 69125874 T DE69125874 T DE 69125874T DE 69125874 T DE69125874 T DE 69125874T DE 69125874 D1 DE69125874 D1 DE 69125874D1
Authority
DE
Germany
Prior art keywords
arrangement
controlling
same
address generator
dimensional address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125874T
Other languages
English (en)
Other versions
DE69125874T2 (de
Inventor
Masaki Toyokura
Kunitoshi Aono
Toshiyuki Araki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69125874D1 publication Critical patent/DE69125874D1/de
Application granted granted Critical
Publication of DE69125874T2 publication Critical patent/DE69125874T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Input (AREA)
  • Image Analysis (AREA)
  • Image Generation (AREA)
DE69125874T 1990-02-21 1991-02-20 Generator für mehrdimensionale Adressen und Anordnung zum Steuern desselben Expired - Fee Related DE69125874T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4142490 1990-02-21

Publications (2)

Publication Number Publication Date
DE69125874D1 true DE69125874D1 (de) 1997-06-05
DE69125874T2 DE69125874T2 (de) 1997-11-20

Family

ID=12607982

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125874T Expired - Fee Related DE69125874T2 (de) 1990-02-21 1991-02-20 Generator für mehrdimensionale Adressen und Anordnung zum Steuern desselben

Country Status (3)

Country Link
US (1) US5293596A (de)
EP (1) EP0443551B1 (de)
DE (1) DE69125874T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398322A (en) * 1990-06-27 1995-03-14 Luminis Pty. Ltd. Number theory mapping generator for addressing matrix structures
JPH0620034A (ja) * 1992-07-02 1994-01-28 Nec Corp 画像処理用アドレス生成回路
JP2677969B2 (ja) * 1993-12-27 1997-11-17 松下電器産業株式会社 直交変換装置
GB9605853D0 (en) * 1996-03-20 1996-05-22 Univ Strathclyde Array indexing
US6055619A (en) * 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6259957B1 (en) 1997-04-04 2001-07-10 Cirrus Logic, Inc. Circuits and methods for implementing audio Codecs and systems using the same
US6427200B1 (en) * 2000-09-27 2002-07-30 Institute For Information Industry Multiple changeable addressing mapping circuit
TW508494B (en) * 2001-03-28 2002-11-01 Shansun Technology Company Data protection device capable of self-defining address arrangement sequence in protection area of storage device
US7958374B2 (en) 2002-03-19 2011-06-07 Shansun Technology Company Digital information protecting method and apparatus, and computer accessible recording medium
US9081725B2 (en) 2002-03-19 2015-07-14 Shansun Technology Company Digital information protecting method and apparatus, and computer accessible recording medium
US7830393B2 (en) * 2004-10-13 2010-11-09 Panasonic Corporation Device, method, and integrated circuit for rectangular image drawing
CN100538886C (zh) * 2005-03-04 2009-09-09 中国科学院计算技术研究所 多维数组在动态随机存取存储器上的快速读写方法和装置
KR101270925B1 (ko) * 2005-05-20 2013-06-07 소니 주식회사 신호 처리 장치
KR100868451B1 (ko) * 2007-02-22 2008-11-11 삼성전자주식회사 3-ｄ 주소 매핑을 이용한 메모리 접근 방법
WO2008114322A1 (ja) * 2007-03-20 2008-09-25 Fujitsu Limited 半導体集積回路および半導体メモリのアクセス制御方法
US9003165B2 (en) * 2008-12-09 2015-04-07 Shlomo Selim Rakib Address generation unit using end point patterns to scan multi-dimensional data structures
US12086597B2 (en) * 2021-06-28 2024-09-10 Silicon Laboratories Inc. Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration
US12079630B2 (en) * 2021-06-28 2024-09-03 Silicon Laboratories Inc. Array processor having an instruction sequencer including a program state controller and loop controllers
US20220413850A1 (en) * 2021-06-28 2022-12-29 Silicon Laboratories Inc. Apparatus for Processor with Macro-Instruction and Associated Methods

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809156A (en) * 1984-03-19 1989-02-28 Trw Inc. Address generator circuit
US4704680A (en) * 1984-08-15 1987-11-03 Tektronix, Inc. Address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle
US4819152A (en) * 1985-04-05 1989-04-04 Raytheon Company Method and apparatus for addressing a memory by array transformations
US4860109A (en) * 1987-01-07 1989-08-22 Matsushita Electric Industrial Co., Ltd. Image processing apparatus
JPH01171067A (ja) * 1987-12-26 1989-07-06 Fanuc Ltd アドレス変換回路

Also Published As

Publication number Publication date
EP0443551B1 (de) 1997-05-02
US5293596A (en) 1994-03-08
DE69125874T2 (de) 1997-11-20
EP0443551A2 (de) 1991-08-28
EP0443551A3 (en) 1992-01-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee