DE69108281D1 - CMOS in ECL Pegelwandler für digitale Signale. - Google Patents

CMOS in ECL Pegelwandler für digitale Signale.

Info

Publication number
DE69108281D1
DE69108281D1 DE69108281T DE69108281T DE69108281D1 DE 69108281 D1 DE69108281 D1 DE 69108281D1 DE 69108281 T DE69108281 T DE 69108281T DE 69108281 T DE69108281 T DE 69108281T DE 69108281 D1 DE69108281 D1 DE 69108281D1
Authority
DE
Germany
Prior art keywords
cmos
digital signals
level converter
ecl level
ecl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69108281T
Other languages
English (en)
Other versions
DE69108281T2 (de
Inventor
Gonzalez Jose Luis Merino
Saenz Fernando Ortiz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Publication of DE69108281D1 publication Critical patent/DE69108281D1/de
Application granted granted Critical
Publication of DE69108281T2 publication Critical patent/DE69108281T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017527—Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage
DE1991608281 1990-04-30 1991-04-20 CMOS in ECL Pegelwandler für digitale Signale. Expired - Fee Related DE69108281T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9001241A ES2022019A6 (es) 1990-04-30 1990-04-30 Conversor de niveles de logica complementaria metal-oxido-semiconductor (cmos) a logica de emisores acoplados (ecl) de senales digitales.

Publications (2)

Publication Number Publication Date
DE69108281D1 true DE69108281D1 (de) 1995-04-27
DE69108281T2 DE69108281T2 (de) 1995-11-23

Family

ID=8267137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1991608281 Expired - Fee Related DE69108281T2 (de) 1990-04-30 1991-04-20 CMOS in ECL Pegelwandler für digitale Signale.

Country Status (4)

Country Link
EP (1) EP0455079B1 (de)
DE (1) DE69108281T2 (de)
DK (1) DK0455079T3 (de)
ES (1) ES2022019A6 (de)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656372A (en) * 1985-11-25 1987-04-07 Ncr Corporation CMOS to ECL interface circuit
US4912347A (en) * 1987-08-25 1990-03-27 American Telephone And Telegraph Company, At&T Bell Laboratories CMOS to ECL output buffer
US4890019A (en) * 1988-09-20 1989-12-26 Digital Equipment Corporation Bilingual CMOS to ECL output buffer

Also Published As

Publication number Publication date
ES2022019A6 (es) 1991-11-16
DK0455079T3 (da) 1995-06-06
DE69108281T2 (de) 1995-11-23
EP0455079B1 (de) 1995-03-22
EP0455079A1 (de) 1991-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee