DE69021965D1 - Reproduziereinrichtung für digitale Signale. - Google Patents

Reproduziereinrichtung für digitale Signale.

Info

Publication number
DE69021965D1
DE69021965D1 DE69021965T DE69021965T DE69021965D1 DE 69021965 D1 DE69021965 D1 DE 69021965D1 DE 69021965 T DE69021965 T DE 69021965T DE 69021965 T DE69021965 T DE 69021965T DE 69021965 D1 DE69021965 D1 DE 69021965D1
Authority
DE
Germany
Prior art keywords
digital signals
reproduction device
reproduction
digital
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69021965T
Other languages
English (en)
Other versions
DE69021965T2 (de
Inventor
Seiichiro Satomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69021965D1 publication Critical patent/DE69021965D1/de
Publication of DE69021965T2 publication Critical patent/DE69021965T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69021965T 1989-06-29 1990-06-28 Reproduziereinrichtung für digitale Signale. Expired - Fee Related DE69021965T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1165290A JPH0332132A (ja) 1989-06-29 1989-06-29 デジタル信号復号装置

Publications (2)

Publication Number Publication Date
DE69021965D1 true DE69021965D1 (de) 1995-10-05
DE69021965T2 DE69021965T2 (de) 1996-02-22

Family

ID=15809520

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69021965T Expired - Fee Related DE69021965T2 (de) 1989-06-29 1990-06-28 Reproduziereinrichtung für digitale Signale.

Country Status (4)

Country Link
US (1) US5231650A (de)
EP (1) EP0407094B1 (de)
JP (1) JPH0332132A (de)
DE (1) DE69021965T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2694403B2 (ja) * 1991-12-13 1997-12-24 シャープ株式会社 ディジタルデータ検出器
JP3352132B2 (ja) * 1992-12-11 2002-12-03 キヤノン株式会社 光学的情報再生装置
JP2636677B2 (ja) * 1993-06-02 1997-07-30 日本電気株式会社 半導体集積回路
US5654842A (en) * 1994-08-30 1997-08-05 Sony Corporation Head displacement measuring method and apparatus and data recording/reproducing method and apparatus
US5859881A (en) * 1996-06-07 1999-01-12 International Business Machines Corporation Adaptive filtering method and apparatus to compensate for a frequency difference between two clock sources
US5757297A (en) * 1996-06-07 1998-05-26 International Business Machines Corporation Method and apparatus for recovering a serial data stream using a local clock
US6067335A (en) * 1996-08-02 2000-05-23 Silicon Systems, Inc. Read channel IC for dual PLL solution
JPH10106146A (ja) * 1996-09-25 1998-04-24 Victor Co Of Japan Ltd ディスクの記録再生方法及び再生装置
US7664214B2 (en) * 2002-09-24 2010-02-16 Standard Microsystems Corporation System and method for transferring data among transceivers substantially void of data dependent jitter
TW589831B (en) * 2002-12-05 2004-06-01 Via Tech Inc Multi-port network interface circuit and related method for triggering transmission signals of multiple ports with clocks of different phases

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2408891A1 (fr) * 1977-11-14 1979-06-08 Cii Honeywell Bull Dispositif d'integration d'une suite de signaux electriques
US4280224A (en) * 1979-06-21 1981-07-21 Ford Aerospace & Communications Corporation Bit synchronizer with early and late gating
US4611335A (en) * 1981-09-30 1986-09-09 Hitachi, Ltd. Digital data synchronizing circuit
US4482927A (en) * 1982-01-15 1984-11-13 Sperry Corporation Ternary magnetic recording and reproducing system with simultaneous overwrite
US4546394A (en) * 1982-01-29 1985-10-08 Sansui Electric Co., Ltd. Signal reconstruction circuit for digital signals
JPH0721943B2 (ja) * 1984-06-30 1995-03-08 株式会社東芝 デ−タ復調方式
US4615037A (en) * 1985-01-29 1986-09-30 Ampex Corporation Phase scatter detection and reduction circuit and method
DE3533467C2 (de) * 1985-09-19 1999-01-21 Tandberg Data Verfahren und Anordnung zum störsicheren Erkennen von in Datensignalen enthaltenen Daten
US4896025A (en) * 1986-02-20 1990-01-23 Canon Kabushiki Kaisha Information reproducing apparatus for information recording medium having a plurality of information tracks
JPH0656958B2 (ja) * 1986-07-03 1994-07-27 キヤノン株式会社 情報デ−タ復元装置
US4872155A (en) * 1987-03-13 1989-10-03 Pioneer Electronic Corporation Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock
US4979189A (en) * 1989-08-18 1990-12-18 National Semiconductor Corporation Self-timing qualification channel

Also Published As

Publication number Publication date
EP0407094A3 (en) 1991-04-17
EP0407094B1 (de) 1995-08-30
US5231650A (en) 1993-07-27
EP0407094A2 (de) 1991-01-09
JPH0332132A (ja) 1991-02-12
DE69021965T2 (de) 1996-02-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee