DE69029791T2 - Nichtflüchtige Speicheranordnung und Betriebsverfahren - Google Patents

Nichtflüchtige Speicheranordnung und Betriebsverfahren

Info

Publication number
DE69029791T2
DE69029791T2 DE69029791T DE69029791T DE69029791T2 DE 69029791 T2 DE69029791 T2 DE 69029791T2 DE 69029791 T DE69029791 T DE 69029791T DE 69029791 T DE69029791 T DE 69029791T DE 69029791 T2 DE69029791 T2 DE 69029791T2
Authority
DE
Germany
Prior art keywords
memory device
volatile memory
operating method
operating
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69029791T
Other languages
English (en)
Other versions
DE69029791D1 (de
Inventor
Carl Michael Stanchak
Raymond Alexander Turi
James Peter Yakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MagnaChip Semiconductor Ltd
NCR International Inc
Original Assignee
NCR International Inc
Hyundai Electronics America Inc
Symbios Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc, Hyundai Electronics America Inc, Symbios Logic Inc filed Critical NCR International Inc
Application granted granted Critical
Publication of DE69029791D1 publication Critical patent/DE69029791D1/de
Publication of DE69029791T2 publication Critical patent/DE69029791T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
DE69029791T 1989-11-29 1990-11-06 Nichtflüchtige Speicheranordnung und Betriebsverfahren Expired - Lifetime DE69029791T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/442,809 US5168464A (en) 1989-11-29 1989-11-29 Nonvolatile differential memory device and method

Publications (2)

Publication Number Publication Date
DE69029791D1 DE69029791D1 (de) 1997-03-13
DE69029791T2 true DE69029791T2 (de) 1997-08-07

Family

ID=23758233

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029791T Expired - Lifetime DE69029791T2 (de) 1989-11-29 1990-11-06 Nichtflüchtige Speicheranordnung und Betriebsverfahren

Country Status (4)

Country Link
US (1) US5168464A (de)
EP (1) EP0430455B1 (de)
JP (1) JP3090329B2 (de)
DE (1) DE69029791T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69426845T2 (de) * 1993-06-30 2001-09-13 St Microelectronics Inc Verfahren und Einrichtung zur Parallelprüfung von Speichern
US6639840B1 (en) * 2002-01-03 2003-10-28 Fairchild Semiconductor Corporation Non-volatile latch circuit that has minimal control circuitry
US7212446B2 (en) * 2002-09-16 2007-05-01 Impinj, Inc. Counteracting overtunneling in nonvolatile memory cells using charge extraction control
JP4167567B2 (ja) 2003-09-01 2008-10-15 松下電器産業株式会社 半導体集積回路装置及びその検査方法
US7283390B2 (en) 2004-04-21 2007-10-16 Impinj, Inc. Hybrid non-volatile memory
US8111558B2 (en) * 2004-05-05 2012-02-07 Synopsys, Inc. pFET nonvolatile memory
US7894261B1 (en) 2008-05-22 2011-02-22 Synopsys, Inc. PFET nonvolatile memory

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130292A (en) * 1981-02-05 1982-08-12 Toshiba Corp Semiconductor nonvolatile read-only storage device
US4404475A (en) * 1981-04-08 1983-09-13 Xicor, Inc. Integrated circuit high voltage pulse generator system
US4612630A (en) * 1984-07-27 1986-09-16 Harris Corporation EEPROM margin testing design
US4616245A (en) * 1984-10-29 1986-10-07 Ncr Corporation Direct-write silicon nitride EEPROM cell
US4644196A (en) * 1985-01-28 1987-02-17 Motorola, Inc. Tri-state differential amplifier
US4683554A (en) * 1985-09-13 1987-07-28 Ncr Corporation Direct write nonvolatile memory cells
US4780750A (en) * 1986-01-03 1988-10-25 Sierra Semiconductor Corporation Electrically alterable non-volatile memory device
US4658380A (en) * 1986-02-28 1987-04-14 Ncr Corporation CMOS memory margining control circuit for a nonvolatile memory
US4748593A (en) * 1986-09-08 1988-05-31 Ncr Corporation High speed nonvolatile memory cell
US4769788A (en) * 1986-09-22 1988-09-06 Ncr Corporation Shared line direct write nonvolatile memory cell array
IT1214246B (it) * 1987-05-27 1990-01-10 Sgs Microelettronica Spa Dispositivo di memoria non volatile ad elevato numero di cicli di modifica.
US4875188A (en) * 1988-01-12 1989-10-17 Intel Corporation Voltage margining circuit for flash eprom
US4841482A (en) * 1988-02-17 1989-06-20 Intel Corporation Leakage verification for flash EPROM

Also Published As

Publication number Publication date
EP0430455A3 (en) 1992-08-26
DE69029791D1 (de) 1997-03-13
EP0430455B1 (de) 1997-01-22
JP3090329B2 (ja) 2000-09-18
JPH03178099A (ja) 1991-08-02
EP0430455A2 (de) 1991-06-05
US5168464A (en) 1992-12-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US

8327 Change in the person/name/address of the patent owner

Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US