DE69027836T2 - Verfahren zur herstellung von halbleiteranordnungen - Google Patents

Verfahren zur herstellung von halbleiteranordnungen

Info

Publication number
DE69027836T2
DE69027836T2 DE69027836T DE69027836T DE69027836T2 DE 69027836 T2 DE69027836 T2 DE 69027836T2 DE 69027836 T DE69027836 T DE 69027836T DE 69027836 T DE69027836 T DE 69027836T DE 69027836 T2 DE69027836 T2 DE 69027836T2
Authority
DE
Germany
Prior art keywords
producing semiconductor
semiconductor arrangements
arrangements
producing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69027836T
Other languages
English (en)
Other versions
DE69027836D1 (de
Inventor
Hidetoshi Oki Electr Wakamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69027836D1 publication Critical patent/DE69027836D1/de
Publication of DE69027836T2 publication Critical patent/DE69027836T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/035—Diffusion through a layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE69027836T 1989-03-23 1990-03-20 Verfahren zur herstellung von halbleiteranordnungen Expired - Fee Related DE69027836T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6935389 1989-03-23
PCT/JP1990/000372 WO1990011618A1 (en) 1989-03-23 1990-03-20 Method of producing semiconductor devices

Publications (2)

Publication Number Publication Date
DE69027836D1 DE69027836D1 (de) 1996-08-22
DE69027836T2 true DE69027836T2 (de) 1997-03-06

Family

ID=13400111

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69027836T Expired - Fee Related DE69027836T2 (de) 1989-03-23 1990-03-20 Verfahren zur herstellung von halbleiteranordnungen

Country Status (5)

Country Link
US (1) US5120677A (de)
EP (1) EP0428732B1 (de)
KR (1) KR0131605B1 (de)
DE (1) DE69027836T2 (de)
WO (1) WO1990011618A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466636A (en) * 1992-09-17 1995-11-14 International Business Machines Corporation Method of forming borderless contacts using a removable mandrel
US5492853A (en) * 1994-03-11 1996-02-20 Micron Semiconductor, Inc. Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device
US6168986B1 (en) * 1998-01-23 2001-01-02 Micron Technology, Inc. Method of making a sacrificial self-aligned interconnect structure
US6107135A (en) * 1998-02-11 2000-08-22 Kabushiki Kaisha Toshiba Method of making a semiconductor memory device having a buried plate electrode
JP2009021502A (ja) * 2007-07-13 2009-01-29 Elpida Memory Inc 半導体装置およびその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798081A (en) * 1972-02-14 1974-03-19 Ibm Method for diffusing as into silicon from a solid phase
JPS5145951B2 (de) * 1972-06-07 1976-12-06
US3789023A (en) * 1972-08-09 1974-01-29 Motorola Inc Liquid diffusion dopant source for semiconductors
JPS5346272A (en) * 1976-10-08 1978-04-25 Nec Corp Impurity diffusion method
US4521441A (en) * 1983-12-19 1985-06-04 Motorola, Inc. Plasma enhanced diffusion process
JPS6239050A (ja) * 1985-08-14 1987-02-20 Hitachi Ltd 半導体装置およびその製造方法
NL8600022A (nl) * 1986-01-08 1987-08-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een doteringselement vanuit zijn oxide in een halfgeleiderlichaam wordt gediffundeerd.
JPH0685429B2 (ja) * 1986-04-10 1994-10-26 日本電気株式会社 半導体記憶装置の製造方法
JPS6384149A (ja) * 1986-09-29 1988-04-14 Hitachi Ltd 半導体メモリの製造方法
US4785337A (en) * 1986-10-17 1988-11-15 International Business Machines Corporation Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes
US4755486A (en) * 1986-12-11 1988-07-05 Siemens Aktiengesellschaft Method of producing a defined arsenic doping in silicon semiconductor substrates

Also Published As

Publication number Publication date
EP0428732B1 (de) 1996-07-17
EP0428732A4 (en) 1991-07-03
WO1990011618A1 (en) 1990-10-04
US5120677A (en) 1992-06-09
KR920700478A (ko) 1992-02-19
DE69027836D1 (de) 1996-08-22
EP0428732A1 (de) 1991-05-29
KR0131605B1 (ko) 1998-04-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee