DE69020331D1 - Halbleiteranordnung, die auf einem Siliziumsubstrat oder auf einer Siliziumschicht gebildet wird, und Verfahren zu deren Herstellung. - Google Patents

Halbleiteranordnung, die auf einem Siliziumsubstrat oder auf einer Siliziumschicht gebildet wird, und Verfahren zu deren Herstellung.

Info

Publication number
DE69020331D1
DE69020331D1 DE69020331T DE69020331T DE69020331D1 DE 69020331 D1 DE69020331 D1 DE 69020331D1 DE 69020331 T DE69020331 T DE 69020331T DE 69020331 T DE69020331 T DE 69020331T DE 69020331 D1 DE69020331 D1 DE 69020331D1
Authority
DE
Germany
Prior art keywords
production
semiconductor device
silicon substrate
silicon
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69020331T
Other languages
English (en)
Other versions
DE69020331T2 (de
Inventor
Takashi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69020331D1 publication Critical patent/DE69020331D1/de
Publication of DE69020331T2 publication Critical patent/DE69020331T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)
DE69020331T 1990-03-30 1990-10-29 Halbleiteranordnung, die auf einem Siliziumsubstrat oder auf einer Siliziumschicht gebildet wird, und Verfahren zu deren Herstellung. Expired - Fee Related DE69020331T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2086715A JP2557546B2 (ja) 1990-03-30 1990-03-30 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69020331D1 true DE69020331D1 (de) 1995-07-27
DE69020331T2 DE69020331T2 (de) 1996-03-07

Family

ID=13894594

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69020331T Expired - Fee Related DE69020331T2 (de) 1990-03-30 1990-10-29 Halbleiteranordnung, die auf einem Siliziumsubstrat oder auf einer Siliziumschicht gebildet wird, und Verfahren zu deren Herstellung.

Country Status (4)

Country Link
US (1) US5136347A (de)
EP (1) EP0450228B1 (de)
JP (1) JP2557546B2 (de)
DE (1) DE69020331T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300788A (en) * 1991-01-18 1994-04-05 Kopin Corporation Light emitting diode bars and arrays and method of making same
JPH06232099A (ja) 1992-09-10 1994-08-19 Mitsubishi Electric Corp 半導体装置の製造方法，半導体装置の製造装置，半導体レーザの製造方法，量子細線構造の製造方法，及び結晶成長方法
US5306386A (en) * 1993-04-06 1994-04-26 Hughes Aircraft Company Arsenic passivation for epitaxial deposition of ternary chalcogenide semiconductor films onto silicon substrates
FR2756972B1 (fr) * 1996-12-10 1999-03-05 France Telecom Procede de relaxation de film contraint par fusion de couche interfaciale
US7872252B2 (en) * 2006-08-11 2011-01-18 Cyrium Technologies Incorporated Method of fabricating semiconductor devices on a group IV substrate with controlled interface properties and diffusion tails
US8362460B2 (en) 2006-08-11 2013-01-29 Cyrium Technologies Incorporated Method of fabricating semiconductor devices on a group IV substrate with controlled interface properties and diffusion tails
US9299560B2 (en) * 2012-01-13 2016-03-29 Applied Materials, Inc. Methods for depositing group III-V layers on substrates
GB201213673D0 (en) 2012-08-01 2012-09-12 Ucl Business Plc Semiconductor device and fabrication method
US20170352536A1 (en) * 2014-12-23 2017-12-07 Integrated Solar A method of epitaxial growth of a material interface between group iii-v materials and silicon wafers providing counterbalancing of residual strains
US9508550B2 (en) * 2015-04-28 2016-11-29 International Business Machines Corporation Preparation of low defect density of III-V on Si for device fabrication

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6191098A (ja) * 1984-10-09 1986-05-09 Daido Steel Co Ltd シリコン基板上における砒素化ガリウム成長結晶体とその結晶成長方法
GB2189345A (en) * 1986-04-16 1987-10-21 Philips Electronic Associated High mobility p channel semi conductor devices
JPH0766922B2 (ja) * 1987-07-29 1995-07-19 株式会社村田製作所 半導体装置の製造方法
EP0365875B1 (de) * 1988-10-28 1995-08-09 Texas Instruments Incorporated Abgedeckte Wärmebehandlung
JP2845464B2 (ja) * 1988-12-20 1999-01-13 富士通株式会社 化合物半導体の成長方法
JPH03201425A (ja) * 1989-12-28 1991-09-03 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
EP0450228A2 (de) 1991-10-09
US5136347A (en) 1992-08-04
JP2557546B2 (ja) 1996-11-27
EP0450228A3 (en) 1991-11-27
DE69020331T2 (de) 1996-03-07
EP0450228B1 (de) 1995-06-21
JPH03284834A (ja) 1991-12-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee