DE69015472D1 - Gezielte Metallniederschlagung. - Google Patents

Gezielte Metallniederschlagung.

Info

Publication number
DE69015472D1
DE69015472D1 DE69015472T DE69015472T DE69015472D1 DE 69015472 D1 DE69015472 D1 DE 69015472D1 DE 69015472 T DE69015472 T DE 69015472T DE 69015472 T DE69015472 T DE 69015472T DE 69015472 D1 DE69015472 D1 DE 69015472D1
Authority
DE
Germany
Prior art keywords
metal precipitation
targeted metal
targeted
precipitation
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015472T
Other languages
English (en)
Other versions
DE69015472T2 (de
Inventor
Gangadhara Swani Mathad
David Stanasolovich
Giorgia Giulio Via
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69015472D1 publication Critical patent/DE69015472D1/de
Application granted granted Critical
Publication of DE69015472T2 publication Critical patent/DE69015472T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12389—All metal or with adjacent metals having variation in thickness
    • Y10T428/12396—Discontinuous surface component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31721—Of polyimide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69015472T 1989-07-06 1990-05-12 Gezielte Metallniederschlagung. Expired - Fee Related DE69015472T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/350,182 US5024896A (en) 1989-07-06 1989-07-06 Collimated metal deposition

Publications (2)

Publication Number Publication Date
DE69015472D1 true DE69015472D1 (de) 1995-02-09
DE69015472T2 DE69015472T2 (de) 1995-07-20

Family

ID=23375556

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015472T Expired - Fee Related DE69015472T2 (de) 1989-07-06 1990-05-12 Gezielte Metallniederschlagung.

Country Status (4)

Country Link
US (1) US5024896A (de)
EP (1) EP0406544B1 (de)
JP (1) JPH0652734B2 (de)
DE (1) DE69015472T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258264A (en) * 1989-07-06 1993-11-02 International Business Machines Corporation Process of forming a dual overhang collimated lift-off stencil with subsequent metal deposition
US5320934A (en) * 1991-06-28 1994-06-14 Misium George R Bilayer photolithographic process
US5221596A (en) * 1991-09-03 1993-06-22 Motorola, Inc. Method of forming a retrograde photoresist profile
JP2951504B2 (ja) * 1992-06-05 1999-09-20 シャープ株式会社 シリル化平坦化レジスト及び平坦化方法並びに集積回路デバイスの製造方法
JP2569405Y2 (ja) * 1993-02-03 1998-04-22 池田物産株式会社 スペアタイヤカバー装置
JPH0660548U (ja) * 1993-02-03 1994-08-23 池田物産株式会社 スペアタイヤカバー装置
AU5926396A (en) * 1995-05-22 1996-12-11 Dynaco Corporation Rigid-flex printed circuit boards
KR19980064444A (ko) * 1996-12-20 1998-10-07 윌리엄비.켐플러 다층 집적 회로 유전체 구조의 에칭 방법
DE19717363C2 (de) * 1997-04-24 2001-09-06 Siemens Ag Herstellverfahren für eine Platinmetall-Struktur mittels eines Lift-off-Prozesses und Verwendung des Herstellverfahrens
US7070697B2 (en) * 2003-04-14 2006-07-04 Hitachi Global Storage Technologies Netherlands B.V. Methods of making a read sensor with use of a barrier structure for depositing materials
JP2010040616A (ja) * 2008-08-01 2010-02-18 Opnext Japan Inc 電極形成方法および半導体素子
US8233248B1 (en) * 2009-09-16 2012-07-31 Western Digital (Fremont), Llc Method and system for providing a magnetic recording transducer using a line hard mask
US8871102B2 (en) 2011-05-25 2014-10-28 Western Digital (Fremont), Llc Method and system for fabricating a narrow line structure in a magnetic recording head
US8697562B2 (en) 2011-06-23 2014-04-15 Richard L. McCreery Metal contacts for molecular device junctions and surface-diffusion-mediated deposition
US9034564B1 (en) 2013-07-26 2015-05-19 Western Digital (Fremont), Llc Reader fabrication method employing developable bottom anti-reflective coating
KR102497358B1 (ko) * 2015-09-24 2023-02-10 주식회사 기가레인 벤딩 내구성이 개선된 연성회로기판
KR102442838B1 (ko) * 2015-09-24 2022-09-15 주식회사 기가레인 3층 유전체 및 4층 그라운드 레이어 구조를 갖는 연성회로기판
KR102432541B1 (ko) * 2015-09-24 2022-08-17 주식회사 기가레인 벤딩 내구성이 개선된 연성회로기판 및 그 제조방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493855A (en) * 1982-12-23 1985-01-15 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks
US4539222A (en) * 1983-11-30 1985-09-03 International Business Machines Corporation Process for forming metal patterns wherein metal is deposited on a thermally depolymerizable polymer and selectively removed
US4519872A (en) * 1984-06-11 1985-05-28 International Business Machines Corporation Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes
US4692205A (en) * 1986-01-31 1987-09-08 International Business Machines Corporation Silicon-containing polyimides as oxygen etch stop and dual dielectric coatings

Also Published As

Publication number Publication date
EP0406544A2 (de) 1991-01-09
EP0406544A3 (en) 1991-03-20
DE69015472T2 (de) 1995-07-20
JPH0652734B2 (ja) 1994-07-06
JPH0346330A (ja) 1991-02-27
EP0406544B1 (de) 1994-12-28
US5024896A (en) 1991-06-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee