DE68928058T2 - Gerät und verfahren zur prädiktion von gleitkommanormalisierung - Google Patents

Gerät und verfahren zur prädiktion von gleitkommanormalisierung

Info

Publication number
DE68928058T2
DE68928058T2 DE68928058T DE68928058T DE68928058T2 DE 68928058 T2 DE68928058 T2 DE 68928058T2 DE 68928058 T DE68928058 T DE 68928058T DE 68928058 T DE68928058 T DE 68928058T DE 68928058 T2 DE68928058 T2 DE 68928058T2
Authority
DE
Germany
Prior art keywords
bit
normalization
result
rounding
amount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928058T
Other languages
German (de)
English (en)
Other versions
DE68928058D1 (de
Inventor
Kathleen Harrington
John Zurawski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE68928058D1 publication Critical patent/DE68928058D1/de
Application granted granted Critical
Publication of DE68928058T2 publication Critical patent/DE68928058T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)
DE68928058T 1988-04-01 1989-03-30 Gerät und verfahren zur prädiktion von gleitkommanormalisierung Expired - Fee Related DE68928058T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/176,612 US4922446A (en) 1988-04-01 1988-04-01 Apparatus and method for floating point normalization prediction
PCT/US1989/001313 WO1989009441A1 (en) 1988-04-01 1989-03-30 Apparatus and method for floating point normalization prediction

Publications (2)

Publication Number Publication Date
DE68928058D1 DE68928058D1 (de) 1997-06-26
DE68928058T2 true DE68928058T2 (de) 1998-01-08

Family

ID=22645091

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928058T Expired - Fee Related DE68928058T2 (de) 1988-04-01 1989-03-30 Gerät und verfahren zur prädiktion von gleitkommanormalisierung

Country Status (6)

Country Link
US (1) US4922446A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0359809B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH02500551A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1311848C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE68928058T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1989009441A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0746310B2 (ja) * 1987-06-30 1995-05-17 三菱電機株式会社 半導体論理回路
US5027308A (en) * 1989-02-14 1991-06-25 Intel Corporation Circuit for adding/subtracting two floating point operands
US5010508A (en) * 1989-02-14 1991-04-23 Intel Corporation Prenormalization for a floating-point adder
JPH0792739B2 (ja) * 1989-05-22 1995-10-09 甲府日本電気株式会社 浮動小数点データ正規化方式
US5144570A (en) * 1989-08-02 1992-09-01 Cyrix Corporation Normalization estimator
JP2831729B2 (ja) * 1989-09-30 1998-12-02 株式会社東芝 プライオリティエンコーダおよび浮動小数点正規化装置
US5231600A (en) * 1990-04-19 1993-07-27 Bull Hn Information Systems Inc. Overflow detector for anticipating producing invalid operands resulting from performing shift operations on such operands
US5150319A (en) * 1991-05-03 1992-09-22 Sun Microsystems, Inc. Circuitry for rounding in a floating point multiplier
US5204825A (en) * 1991-08-30 1993-04-20 Weitek Corporation Method and apparatus for exact leading zero prediction for a floating-point adder
US5408426A (en) * 1992-03-17 1995-04-18 Hitachi, Ltd. Arithmetic unit capable of performing concurrent operations for high speed operation
GB2275355B (en) * 1993-02-19 1997-06-18 Motorola Inc Detection of exponent underflow and overflow in a floating point adder
US5317527A (en) * 1993-02-10 1994-05-31 Digital Equipment Corporation Leading one/zero bit detector for floating point operation
US5530663A (en) * 1994-11-14 1996-06-25 International Business Machines Corporation Floating point unit for calculating a compound instruction A+B×C in two cycles
JP3313002B2 (ja) * 1994-12-02 2002-08-12 三菱電機株式会社 浮動小数点演算装置
US5635858A (en) * 1995-06-07 1997-06-03 International Business Machines, Corporation Zero-stopping incrementers
US5867407A (en) * 1995-06-30 1999-02-02 Digital Equipment Corporation Normalization shift prediction independent of operand substraction
EP1291764A1 (en) * 1995-10-20 2003-03-12 Kabushiki Kaisha Toshiba Logic circuit and method for designing the same
US5764549A (en) * 1996-04-29 1998-06-09 International Business Machines Corporation Fast floating point result alignment apparatus
US6085208A (en) * 1997-10-23 2000-07-04 Advanced Micro Devices, Inc. Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit
US6012076A (en) * 1997-12-29 2000-01-04 Motorola, Inc. Arithmetic logic unit having preshift and preround circuits
US7043516B1 (en) 1998-03-13 2006-05-09 Hewlett-Packard Development Company, L.P. Reduction of add-pipe logic by operand offset shift
US6018756A (en) * 1998-03-13 2000-01-25 Digital Equipment Corporation Reduced-latency floating-point pipeline using normalization shifts of both operands
GB2409074B (en) * 2001-03-14 2005-08-03 Micron Technology Inc Arithmetic pipeline
US6988115B2 (en) 2001-05-04 2006-01-17 Broadcom Corporation Method and apparatus to correct leading one prediction
US6941335B2 (en) * 2001-11-29 2005-09-06 International Business Machines Corporation Random carry-in for floating-point operations
US9996319B2 (en) * 2015-12-23 2018-06-12 Intel Corporation Floating point (FP) add low instructions functional unit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608933A (ja) * 1983-06-28 1985-01-17 Nec Corp 演算処理装置
JPS60124729A (ja) * 1983-12-09 1985-07-03 Fujitsu Ltd 浮動小数点加減算方式
US4758974A (en) * 1985-01-29 1988-07-19 American Telephone And Telegraph Company, At&T Bell Laboratories Most significant digit location
JPH0644225B2 (ja) * 1986-03-27 1994-06-08 日本電気株式会社 浮動小数点丸め正規化回路

Also Published As

Publication number Publication date
EP0359809A1 (en) 1990-03-28
JPH0544046B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-07-05
DE68928058D1 (de) 1997-06-26
JPH02500551A (ja) 1990-02-22
WO1989009441A1 (en) 1989-10-05
CA1311848C (en) 1992-12-22
EP0359809A4 (en) 1992-05-13
EP0359809B1 (en) 1997-05-21
US4922446A (en) 1990-05-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee