DE68923541D1 - Programmierbare Logikeinrichtung mit einer Vielzahl von programmierbaren Logikarrays, die sich in mosaikförmiger Anordnung zusammen mit einer Vielzahl von vermischt angeordneten Interface-Blöcken befinden. - Google Patents
Programmierbare Logikeinrichtung mit einer Vielzahl von programmierbaren Logikarrays, die sich in mosaikförmiger Anordnung zusammen mit einer Vielzahl von vermischt angeordneten Interface-Blöcken befinden.Info
- Publication number
- DE68923541D1 DE68923541D1 DE68923541T DE68923541T DE68923541D1 DE 68923541 D1 DE68923541 D1 DE 68923541D1 DE 68923541 T DE68923541 T DE 68923541T DE 68923541 T DE68923541 T DE 68923541T DE 68923541 D1 DE68923541 D1 DE 68923541D1
- Authority
- DE
- Germany
- Prior art keywords
- multiplicity
- programmable logic
- interface blocks
- mosaic arrangement
- arrangement together
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/54—Ring counters, i.e. feedback shift register counters
- H03K23/542—Ring counters, i.e. feedback shift register counters with crossed-couplings, i.e. Johnson counters
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT8883691A IT1225638B (it) | 1988-12-28 | 1988-12-28 | Dispositivo logico integrato come una rete di maglie di memorie distribuite |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68923541D1 true DE68923541D1 (de) | 1995-08-24 |
DE68923541T2 DE68923541T2 (de) | 1996-02-22 |
Family
ID=11323819
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68923541T Expired - Fee Related DE68923541T2 (de) | 1988-12-28 | 1989-12-22 | Programmierbare Logikeinrichtung mit einer Vielzahl von programmierbaren Logikarrays, die sich in mosaikförmiger Anordnung zusammen mit einer Vielzahl von vermischt angeordneten Interface-Blöcken befinden. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4992680A (de) |
EP (1) | EP0376905B1 (de) |
JP (1) | JPH02226813A (de) |
DE (1) | DE68923541T2 (de) |
IT (1) | IT1225638B (de) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5511211A (en) * | 1988-08-31 | 1996-04-23 | Hitachi, Ltd. | Method for flexibly developing a data processing system comprising rewriting instructions in non-volatile memory elements after function check indicates failure of required functions |
US5198705A (en) * | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
US5073729A (en) * | 1990-06-22 | 1991-12-17 | Actel Corporation | Segmented routing architecture |
US5191241A (en) * | 1990-08-01 | 1993-03-02 | Actel Corporation | Programmable interconnect architecture |
US5144166A (en) * | 1990-11-02 | 1992-09-01 | Concurrent Logic, Inc. | Programmable logic cell and array |
US5079451A (en) * | 1990-12-13 | 1992-01-07 | Atmel Corporation | Programmable logic device with global and local product terms |
US5204556A (en) * | 1991-05-06 | 1993-04-20 | Lattice Semiconductor Corporation | Programmable interconnect structure for logic blocks |
JPH05252025A (ja) * | 1991-10-28 | 1993-09-28 | Texas Instr Inc <Ti> | 論理モジュールおよび集積回路 |
US5412261A (en) * | 1992-04-14 | 1995-05-02 | Aptix Corporation | Two-stage programmable interconnect architecture |
US5369772A (en) * | 1992-05-21 | 1994-11-29 | Compaq Computer Corporation | Method of maximizing data pin usage utilizing post-buffer feedback |
GB9223226D0 (en) | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
AU6958694A (en) * | 1993-05-28 | 1994-12-20 | Regents Of The University Of California, The | Field programmable logic device with dynamic interconnections to a dynamic logic core |
US6462578B2 (en) | 1993-08-03 | 2002-10-08 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6051991A (en) * | 1993-08-03 | 2000-04-18 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
KR19990008270A (ko) | 1995-05-03 | 1999-01-25 | 팅 벤자민 에스. | 스케일가능한 복수 레벨 상호연결 아키텍춰 |
US5850564A (en) * | 1995-05-03 | 1998-12-15 | Btr, Inc, | Scalable multiple level tab oriented interconnect architecture |
US5684413A (en) * | 1996-03-28 | 1997-11-04 | Philips Electronics North America Corp. | Condensed single block PLA plus PAL architecture |
US6034547A (en) * | 1996-09-04 | 2000-03-07 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus |
US6624658B2 (en) | 1999-02-04 | 2003-09-23 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US6005410A (en) * | 1996-12-05 | 1999-12-21 | International Business Machines Corporation | Interconnect structure between heterogeneous core regions in a programmable array |
US5959466A (en) * | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
US5936426A (en) * | 1997-02-03 | 1999-08-10 | Actel Corporation | Logic function module for field programmable array |
US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6150836A (en) * | 1997-06-13 | 2000-11-21 | Malleable Technologies, Inc. | Multilevel logic field programmable device |
US6006321A (en) * | 1997-06-13 | 1999-12-21 | Malleable Technologies, Inc. | Programmable logic datapath that may be used in a field programmable device |
US6407576B1 (en) | 1999-03-04 | 2002-06-18 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6438569B1 (en) | 1999-09-20 | 2002-08-20 | Pmc-Sierra, Inc. | Sums of production datapath |
US6320412B1 (en) | 1999-12-20 | 2001-11-20 | Btr, Inc. C/O Corporate Trust Co. | Architecture and interconnect for programmable logic circuits |
US7255437B2 (en) * | 2003-10-09 | 2007-08-14 | Howell Thomas A | Eyeglasses with activity monitoring |
US6975139B2 (en) * | 2004-03-30 | 2005-12-13 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US7460529B2 (en) * | 2004-07-29 | 2008-12-02 | Advantage Logic, Inc. | Interconnection fabric using switching networks in hierarchy |
US7423453B1 (en) | 2006-01-20 | 2008-09-09 | Advantage Logic, Inc. | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric |
US7999570B2 (en) | 2009-06-24 | 2011-08-16 | Advantage Logic, Inc. | Enhanced permutable switching network with multicasting signals for interconnection fabric |
US9202166B2 (en) * | 2012-11-09 | 2015-12-01 | Colin James, III | Method and system for kanban cell neuron network |
WO2017174788A1 (en) * | 2016-04-07 | 2017-10-12 | Nagravision Sa | Flexible cryptographic device |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5766587A (en) * | 1980-10-09 | 1982-04-22 | Fujitsu Ltd | Static semiconductor storage device |
JPS59119925A (ja) * | 1982-12-27 | 1984-07-11 | Toshiba Corp | 論理回路 |
DE3342354A1 (de) * | 1983-04-14 | 1984-10-18 | Control Data Corp., Minneapolis, Minn. | Weich programmierbare logikanordnung |
US4706216A (en) * | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
KR950015009B1 (ko) * | 1985-09-11 | 1995-12-21 | 필킹톤 마이크로-엘렉트로닉스 리미티드 | 배치가능한 반도체 집적회로 |
EP0257023A1 (de) * | 1986-02-07 | 1988-03-02 | Silicon Communications Corporation | Elektrisch löschbare, programmierbare, logische anordnung (eepla) |
US4772811A (en) * | 1986-07-04 | 1988-09-20 | Ricoh Company, Ltd. | Programmable logic device |
US4910417A (en) * | 1986-09-19 | 1990-03-20 | Actel Corporation | Universal logic module comprising multiplexers |
JPS63151115A (ja) * | 1986-12-15 | 1988-06-23 | Canon Inc | 論理回路装置 |
JPS63316921A (ja) * | 1987-06-19 | 1988-12-26 | Matsushita Electric Ind Co Ltd | ディジタル装置の接続方法 |
JPH088304B2 (ja) * | 1987-08-19 | 1996-01-29 | 富士通株式会社 | 半導体集積回路装置及びその設計方法 |
US4912345A (en) * | 1988-12-29 | 1990-03-27 | Sgs-Thomson Microelectronics, Inc. | Programmable summing functions for programmable logic devices |
JP2666681B2 (ja) * | 1993-06-11 | 1997-10-22 | 日本電気株式会社 | 半導体装置の製造方法 |
-
1988
- 1988-12-28 IT IT8883691A patent/IT1225638B/it active
-
1989
- 1989-12-22 EP EP89830569A patent/EP0376905B1/de not_active Expired - Lifetime
- 1989-12-22 DE DE68923541T patent/DE68923541T2/de not_active Expired - Fee Related
- 1989-12-27 US US07/456,782 patent/US4992680A/en not_active Expired - Lifetime
- 1989-12-28 JP JP1345077A patent/JPH02226813A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0376905B1 (de) | 1995-07-19 |
DE68923541T2 (de) | 1996-02-22 |
US4992680A (en) | 1991-02-12 |
JPH02226813A (ja) | 1990-09-10 |
EP0376905A3 (de) | 1992-05-27 |
IT8883691A0 (it) | 1988-12-28 |
IT1225638B (it) | 1990-11-22 |
EP0376905A2 (de) | 1990-07-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |