DE68923262D1 - Zweierkomplementmultiplikation mit einem Vorzeichen-/Grössen-Multiplizierer. - Google Patents

Zweierkomplementmultiplikation mit einem Vorzeichen-/Grössen-Multiplizierer.

Info

Publication number
DE68923262D1
DE68923262D1 DE68923262T DE68923262T DE68923262D1 DE 68923262 D1 DE68923262 D1 DE 68923262D1 DE 68923262 T DE68923262 T DE 68923262T DE 68923262 T DE68923262 T DE 68923262T DE 68923262 D1 DE68923262 D1 DE 68923262D1
Authority
DE
Germany
Prior art keywords
sign
size multiplier
complement multiplication
multiplication
complement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923262T
Other languages
English (en)
Other versions
DE68923262T2 (de
Inventor
Stamatis Vassiliadis
Eric Mark Schwarz
Baik Moon Sung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68923262D1 publication Critical patent/DE68923262D1/de
Application granted granted Critical
Publication of DE68923262T2 publication Critical patent/DE68923262T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
DE68923262T 1988-12-28 1989-11-24 Zweierkomplementmultiplikation mit einem Vorzeichen-/Grössen-Multiplizierer. Expired - Fee Related DE68923262T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/291,659 US4926371A (en) 1988-12-28 1988-12-28 Two's complement multiplication with a sign magnitude multiplier

Publications (2)

Publication Number Publication Date
DE68923262D1 true DE68923262D1 (de) 1995-08-03
DE68923262T2 DE68923262T2 (de) 1996-02-15

Family

ID=23121253

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923262T Expired - Fee Related DE68923262T2 (de) 1988-12-28 1989-11-24 Zweierkomplementmultiplikation mit einem Vorzeichen-/Grössen-Multiplizierer.

Country Status (4)

Country Link
US (1) US4926371A (de)
EP (1) EP0375947B1 (de)
JP (1) JPH0727458B2 (de)
DE (1) DE68923262T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5303176A (en) * 1992-07-20 1994-04-12 International Business Machines Corporation High performance array multiplier using four-to-two composite counters
KR0158647B1 (ko) * 1995-05-22 1998-12-15 윤종용 부호/무부호 수 겸용 곱셈기
US5870322A (en) * 1995-05-22 1999-02-09 Samsung Electronics Co., Ltd. Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication
US5646877A (en) * 1995-05-25 1997-07-08 Texas Instruments Incorporated High radix multiplier architecture
US6073156A (en) * 1998-06-19 2000-06-06 Ati International Srl Circuit and method for wrap-around sign extension for signed numbers using replacement of most significant bit
US6081823A (en) * 1998-06-19 2000-06-27 Ati International Srl Circuit and method for wrap-around sign extension for signed numbers
US6421698B1 (en) * 1998-11-04 2002-07-16 Teleman Multimedia, Inc. Multipurpose processor for motion estimation, pixel processing, and general processing
US7003543B2 (en) * 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6975679B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US20030005269A1 (en) * 2001-06-01 2003-01-02 Conner Joshua M. Multi-precision barrel shifting
US6976158B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US6934728B2 (en) * 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US20020184566A1 (en) * 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6985986B2 (en) * 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US20030005268A1 (en) * 2001-06-01 2003-01-02 Catherwood Michael I. Find first bit value instruction
US20030028696A1 (en) * 2001-06-01 2003-02-06 Michael Catherwood Low overhead interrupt
US6952711B2 (en) * 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US7020788B2 (en) * 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US6937084B2 (en) * 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US7467178B2 (en) * 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US7007172B2 (en) * 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US20030023836A1 (en) * 2001-06-01 2003-01-30 Michael Catherwood Shadow register array control instructions
US8234319B2 (en) * 2005-05-25 2012-07-31 Qualcomm Incorporated System and method of performing two's complement operations in a digital signal processor
US11301542B2 (en) * 2019-05-15 2022-04-12 Nxp B.V. Methods and apparatuses involving fast fourier transforms processing of data in a signed magnitude form

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617723A (en) * 1970-02-25 1971-11-02 Collins Radio Co Digitalized multiplier
US3730425A (en) * 1971-05-03 1973-05-01 Honeywell Inf Systems Binary two{40 s complement multiplier processing two multiplier bits per cycle
US3737638A (en) * 1972-07-18 1973-06-05 Ibm A series-parallel multiplication device using modified two{40 s complement arithmetic
US3805043A (en) * 1972-10-11 1974-04-16 Bell Telephone Labor Inc Serial-parallel binary multiplication using pairwise addition
US3866030A (en) * 1974-04-01 1975-02-11 Bell Telephone Labor Inc Two{3 s complement parallel array multiplier
JPS571014B2 (de) * 1974-09-30 1982-01-08
US4153938A (en) * 1977-08-18 1979-05-08 Monolithic Memories Inc. High speed combinatorial digital multiplier
US4130878A (en) * 1978-04-03 1978-12-19 Motorola, Inc. Expandable 4 × 8 array multiplier
NL7809398A (nl) * 1978-09-15 1980-03-18 Philips Nv Vermenigvuldiginrichting voor binaire getallen in twee-complement notatie.
JPS5899839A (ja) * 1981-12-10 1983-06-14 Toshiba Corp 符号付き乗算補正回路
US4594679A (en) * 1983-07-21 1986-06-10 International Business Machines Corporation High speed hardware multiplier for fixed floating point operands
JPS60163128A (ja) * 1984-02-02 1985-08-26 Nec Corp 乗算回路
US4748582A (en) * 1985-06-19 1988-05-31 Advanced Micro Devices, Inc. Parallel multiplier array with foreshortened sign extension
JPH069028B2 (ja) * 1986-02-18 1994-02-02 日本電気株式会社 演算装置
US4796219A (en) * 1987-06-01 1989-01-03 Motorola, Inc. Serial two's complement multiplier

Also Published As

Publication number Publication date
JPH0727458B2 (ja) 1995-03-29
US4926371A (en) 1990-05-15
EP0375947B1 (de) 1995-06-28
JPH02202632A (ja) 1990-08-10
EP0375947A2 (de) 1990-07-04
DE68923262T2 (de) 1996-02-15
EP0375947A3 (de) 1992-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee