DE68910375T2 - Rekursiver Addierer zur Berechnung der Summe zweier Operanden. - Google Patents

Rekursiver Addierer zur Berechnung der Summe zweier Operanden.

Info

Publication number
DE68910375T2
DE68910375T2 DE89400604T DE68910375T DE68910375T2 DE 68910375 T2 DE68910375 T2 DE 68910375T2 DE 89400604 T DE89400604 T DE 89400604T DE 68910375 T DE68910375 T DE 68910375T DE 68910375 T2 DE68910375 T2 DE 68910375T2
Authority
DE
Germany
Prior art keywords
operands
sum
calculating
recursive adder
recursive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89400604T
Other languages
English (en)
Other versions
DE68910375D1 (de
Inventor
Francis Jutand
Luc Montperrus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Application granted granted Critical
Publication of DE68910375D1 publication Critical patent/DE68910375D1/de
Publication of DE68910375T2 publication Critical patent/DE68910375T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE89400604T 1988-03-07 1989-03-03 Rekursiver Addierer zur Berechnung der Summe zweier Operanden. Expired - Fee Related DE68910375T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8802867A FR2628232B1 (fr) 1988-03-07 1988-03-07 Additionneur de type recursif pour calculer la somme de deux operandes

Publications (2)

Publication Number Publication Date
DE68910375D1 DE68910375D1 (de) 1993-12-09
DE68910375T2 true DE68910375T2 (de) 1994-05-11

Family

ID=9363972

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89400604T Expired - Fee Related DE68910375T2 (de) 1988-03-07 1989-03-03 Rekursiver Addierer zur Berechnung der Summe zweier Operanden.

Country Status (5)

Country Link
US (1) US4942549A (de)
EP (1) EP0341097B1 (de)
JP (1) JPH02153424A (de)
DE (1) DE68910375T2 (de)
FR (1) FR2628232B1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8904392D0 (en) * 1989-02-27 1989-04-12 Ibm An arithmetic logic unit for a graphics processor
JPH0391832A (ja) * 1989-09-05 1991-04-17 Sony Corp 加算回路
KR100197354B1 (ko) * 1995-06-28 1999-06-15 김영환 클럭 위상을 이용한 캐리증가 가산기
JPH09231055A (ja) * 1996-02-27 1997-09-05 Denso Corp 論理演算回路及びキャリールックアヘッド加算器
DE10215785A1 (de) * 2002-04-10 2003-10-30 Infineon Technologies Ag Rechenwerk und Verfahren zum Addieren
DE10215784A1 (de) * 2002-04-10 2003-10-30 Infineon Technologies Ag Rechenwerk und Verfahren zum Subtrahieren

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0164450B1 (de) * 1983-12-27 1990-03-07 Nec Corporation Eine, für eine arithmetische Operation hoher Geschwindigkeit geeignete, Übertragsschaltung
JPS6149233A (ja) * 1984-08-17 1986-03-11 Nec Corp 高速デジタル加減算回路
US4623982A (en) * 1985-06-10 1986-11-18 Hewlett-Packard Company Conditional carry techniques for digital processors

Also Published As

Publication number Publication date
EP0341097B1 (de) 1993-11-03
DE68910375D1 (de) 1993-12-09
JPH02153424A (ja) 1990-06-13
FR2628232A1 (fr) 1989-09-08
FR2628232B1 (fr) 1994-04-08
US4942549A (en) 1990-07-17
EP0341097A1 (de) 1989-11-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee