DE60336021D1 - Mehrphasentaktwiedergewinnung - Google Patents

Mehrphasentaktwiedergewinnung

Info

Publication number
DE60336021D1
DE60336021D1 DE60336021T DE60336021T DE60336021D1 DE 60336021 D1 DE60336021 D1 DE 60336021D1 DE 60336021 T DE60336021 T DE 60336021T DE 60336021 T DE60336021 T DE 60336021T DE 60336021 D1 DE60336021 D1 DE 60336021D1
Authority
DE
Germany
Prior art keywords
clock
input data
vector
sample
data transition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60336021T
Other languages
English (en)
Inventor
Jesper Fredriksson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Application granted granted Critical
Publication of DE60336021D1 publication Critical patent/DE60336021D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
DE60336021T 2003-04-29 2003-04-29 Mehrphasentaktwiedergewinnung Expired - Lifetime DE60336021D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2003/000699 WO2004105303A1 (en) 2003-04-29 2003-04-29 Multiphase clock recovery

Publications (1)

Publication Number Publication Date
DE60336021D1 true DE60336021D1 (de) 2011-03-24

Family

ID=33476137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60336021T Expired - Lifetime DE60336021D1 (de) 2003-04-29 2003-04-29 Mehrphasentaktwiedergewinnung

Country Status (6)

Country Link
US (1) US7567629B2 (de)
EP (1) EP1620968B1 (de)
AT (1) ATE498257T1 (de)
AU (1) AU2003230507A1 (de)
DE (1) DE60336021D1 (de)
WO (1) WO2004105303A1 (de)

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US7558317B2 (en) * 2005-04-29 2009-07-07 Hewlett-Packard Development Company, L.P. Edge calibration for synchronous data transfer between clock domains
US7711063B2 (en) * 2005-06-10 2010-05-04 Rambus, Inc. Digital transmitter with data stream transformation circuitry
US20090265485A1 (en) * 2005-11-30 2009-10-22 Broadcom Corporation Ring-based cache coherent bus
EP2360844B1 (de) 2006-04-26 2014-07-23 Qualcomm Incorporated Kommunikation mit drahtloser Vorrichtung mit mehreren Peripheriegeräten
KR100834393B1 (ko) * 2006-10-31 2008-06-04 주식회사 하이닉스반도체 클럭 데이터 복원장치.
CN101399757B (zh) * 2007-09-25 2011-02-02 华为技术有限公司 跟踪时钟源的方法和装置
US7949679B2 (en) * 2008-03-05 2011-05-24 International Business Machines Corporation Efficient storage for finite state machines
US8798530B2 (en) * 2009-06-30 2014-08-05 Oracle America, Inc. Adaptive offset-compensating decision-feedback receiver
US8401135B2 (en) * 2010-02-02 2013-03-19 International Business Machines Corporation Post-equalization amplitude latch-based channel characteristic measurement
TWI423588B (zh) * 2010-12-23 2014-01-11 Ind Tech Res Inst 位準變遷判斷電路及其方法
US8666006B1 (en) * 2011-02-25 2014-03-04 SMSC Holdings. S.a.r.l. Systems and methods for high speed data recovery with free running sampling clock
US8744370B2 (en) * 2011-05-18 2014-06-03 Agilent Technologies, Inc. System for characterizing mixer or converter response
US8595546B2 (en) * 2011-10-28 2013-11-26 Zettaset, Inc. Split brain resistant failover in high availability clusters
US9141738B2 (en) * 2012-06-04 2015-09-22 Reveal Design Automation Sequential non-deterministic detection in hardware design
US8970455B2 (en) 2012-06-28 2015-03-03 Google Technology Holdings LLC Systems and methods for processing content displayed on a flexible display
US8837657B1 (en) * 2012-07-18 2014-09-16 Cypress Semiconductor Corporation Multi-phase sampling circuits and methods
US9178433B2 (en) * 2013-05-15 2015-11-03 Bel Fuse (Macao Commercial Offshore) Limited Droop current sharing power converter with controlled transitions between regulation set points
US9137008B2 (en) * 2013-07-23 2015-09-15 Qualcomm Incorporated Three phase clock recovery delay calibration
US9154130B2 (en) * 2014-01-14 2015-10-06 Analog Devices, Inc. Four-state input detection circuitry
US9281934B2 (en) * 2014-05-02 2016-03-08 Qualcomm Incorporated Clock and data recovery with high jitter tolerance and fast phase locking
US9524264B2 (en) 2014-06-26 2016-12-20 Qualcomm Incorporated Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media
US10521397B2 (en) * 2016-12-28 2019-12-31 Hyland Switzerland Sarl System and methods of proactively searching and continuously monitoring content from a plurality of data sources
US11065963B2 (en) * 2017-08-01 2021-07-20 Lg Chem, Ltd. Diagnostic system for a DC-DC voltage converter
US11469919B2 (en) 2020-09-17 2022-10-11 Analog Devices International Unlimited Company Bidirectional communication circuit and a method for operating a bidirectional communication circuit
US11811418B2 (en) * 2022-03-01 2023-11-07 International Business Machines Corporation Analog-to-digital converter circuit with a nested look up table
US11916568B2 (en) 2022-03-01 2024-02-27 International Business Machines Corporation Sampling circuit with a hierarchical time step generator

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US4189622A (en) 1975-10-17 1980-02-19 Ncr Corporation Data communication system and bit-timing circuit
US4415984A (en) 1980-06-25 1983-11-15 Burroughs Corporation Synchronous clock regenerator for binary serial data signals
US4821297A (en) 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
US4977582A (en) 1988-03-31 1990-12-11 At&T Bell Laboratories Synchronization of non-continuous digital bit streams
EP0390958A1 (de) 1989-04-07 1990-10-10 Siemens Aktiengesellschaft Verfahren zur Datentaktregenerierung für Datensignale und Schaltungsanordnung zur Durchführung des Verfahrens
US5185768A (en) 1990-10-09 1993-02-09 International Business Machines Corporation Digital integrating clock extractor
US5197086A (en) * 1990-12-28 1993-03-23 International Business Machines Corporation High speed digital clock synchronizer
US5488641A (en) 1992-12-10 1996-01-30 Northern Telecom Limited Digital phase-locked loop circuit
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US5822386A (en) 1995-11-29 1998-10-13 Lucent Technologies Inc. Phase recovery circuit for high speed and high density applications
IT1284718B1 (it) 1996-07-31 1998-05-21 Cselt Centro Studi Lab Telecom Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati.
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JP3622685B2 (ja) * 2000-10-19 2005-02-23 セイコーエプソン株式会社 サンプリングクロック生成回路、データ転送制御装置及び電子機器
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JP3854883B2 (ja) * 2002-03-22 2006-12-06 株式会社リコー ビット同期回路及び半導体装置
JP4158465B2 (ja) * 2002-09-10 2008-10-01 日本電気株式会社 クロック再生装置、および、クロック再生装置を用いた電子機器

Also Published As

Publication number Publication date
EP1620968B1 (de) 2011-02-09
US20070009066A1 (en) 2007-01-11
WO2004105303A1 (en) 2004-12-02
ATE498257T1 (de) 2011-02-15
US7567629B2 (en) 2009-07-28
AU2003230507A1 (en) 2004-12-13
EP1620968A1 (de) 2006-02-01

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