DE60330968D1 - Dynamisch konfigurierbare Abtastprüfung - Google Patents

Dynamisch konfigurierbare Abtastprüfung

Info

Publication number
DE60330968D1
DE60330968D1 DE60330968T DE60330968T DE60330968D1 DE 60330968 D1 DE60330968 D1 DE 60330968D1 DE 60330968 T DE60330968 T DE 60330968T DE 60330968 T DE60330968 T DE 60330968T DE 60330968 D1 DE60330968 D1 DE 60330968D1
Authority
DE
Germany
Prior art keywords
dynamically configurable
scanning test
configurable scanning
test
dynamically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60330968T
Other languages
English (en)
Inventor
Alessandro Paglieri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments France SAS
Texas Instruments Inc
Original Assignee
Texas Instruments France SAS
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments France SAS, Texas Instruments Inc filed Critical Texas Instruments France SAS
Application granted granted Critical
Publication of DE60330968D1 publication Critical patent/DE60330968D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
DE60330968T 2003-11-27 2003-11-27 Dynamisch konfigurierbare Abtastprüfung Expired - Lifetime DE60330968D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP20030292959 EP1536244B1 (de) 2003-11-27 2003-11-27 Dynamisch konfigurierbare Abtastprüfung

Publications (1)

Publication Number Publication Date
DE60330968D1 true DE60330968D1 (de) 2010-03-04

Family

ID=34443096

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60330968T Expired - Lifetime DE60330968D1 (de) 2003-11-27 2003-11-27 Dynamisch konfigurierbare Abtastprüfung

Country Status (2)

Country Link
EP (1) EP1536244B1 (de)
DE (1) DE60330968D1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1852706B1 (de) 2006-05-04 2009-10-28 STMicroelectronics S.r.l. Adaptive Scan-compression Architektur

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636227A (en) * 1994-07-08 1997-06-03 Advanced Risc Machines Limited Integrated circuit test mechansim and method
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US5831992A (en) * 1995-08-17 1998-11-03 Northern Telecom Limited Methods and apparatus for fault diagnosis in self-testable systems
US6557129B1 (en) * 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses

Also Published As

Publication number Publication date
EP1536244B1 (de) 2010-01-13
EP1536244A1 (de) 2005-06-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition