DE60316774D1 - Verkettung von mehrfadenprozessorkernen zur bearbeitung von datenpaketen - Google Patents

Verkettung von mehrfadenprozessorkernen zur bearbeitung von datenpaketen

Info

Publication number
DE60316774D1
DE60316774D1 DE60316774T DE60316774T DE60316774D1 DE 60316774 D1 DE60316774 D1 DE 60316774D1 DE 60316774 T DE60316774 T DE 60316774T DE 60316774 T DE60316774 T DE 60316774T DE 60316774 D1 DE60316774 D1 DE 60316774D1
Authority
DE
Germany
Prior art keywords
processor core
programming
multiple processor
data packages
machining data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60316774T
Other languages
English (en)
Other versions
DE60316774T2 (de
Inventor
Matthew Adiletta
Debra Bernstein
Hugh Wilkinson
Gilbert Wolrich
Mark Rosenbluth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60316774D1 publication Critical patent/DE60316774D1/de
Application granted granted Critical
Publication of DE60316774T2 publication Critical patent/DE60316774T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Devices For Executing Special Programs (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Multi-Process Working Machines And Systems (AREA)
  • Numerical Control (AREA)
DE60316774T 2002-01-25 2003-01-16 Verkettung von mehrfadenprozessorkernen zur bearbeitung von datenpaketen Expired - Lifetime DE60316774T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US57723 2002-01-25
US10/057,723 US7181594B2 (en) 2002-01-25 2002-01-25 Context pipelines
PCT/US2003/001580 WO2003065207A2 (en) 2002-01-25 2003-01-16 Pipelines of multithreaded processor cores for packet processing

Publications (2)

Publication Number Publication Date
DE60316774D1 true DE60316774D1 (de) 2007-11-22
DE60316774T2 DE60316774T2 (de) 2008-08-28

Family

ID=27609476

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60316774T Expired - Lifetime DE60316774T2 (de) 2002-01-25 2003-01-16 Verkettung von mehrfadenprozessorkernen zur bearbeitung von datenpaketen

Country Status (11)

Country Link
US (1) US7181594B2 (de)
EP (1) EP1481323B1 (de)
KR (1) KR100613923B1 (de)
CN (1) CN100440151C (de)
AT (1) ATE375552T1 (de)
AU (1) AU2003209290A1 (de)
CA (1) CA2473551C (de)
DE (1) DE60316774T2 (de)
HK (1) HK1072298A1 (de)
TW (1) TWI231914B (de)
WO (1) WO2003065207A2 (de)

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US6934951B2 (en) * 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7437724B2 (en) * 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
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US7853951B2 (en) * 2005-07-25 2010-12-14 Intel Corporation Lock sequencing to reorder and grant lock requests from multiple program threads
US20070044103A1 (en) * 2005-07-25 2007-02-22 Mark Rosenbluth Inter-thread communication of lock protected data
US20070124728A1 (en) * 2005-11-28 2007-05-31 Mark Rosenbluth Passing work between threads
US7624250B2 (en) 2005-12-05 2009-11-24 Intel Corporation Heterogeneous multi-core processor having dedicated connections between processor cores
US20070140282A1 (en) * 2005-12-21 2007-06-21 Sridhar Lakshmanamurthy Managing on-chip queues in switched fabric networks
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US8127262B1 (en) * 2008-12-18 2012-02-28 Xilinx, Inc. Communicating state data between stages of pipelined packet processor
US10353826B2 (en) * 2017-07-14 2019-07-16 Arm Limited Method and apparatus for fast context cloning in a data processing system
US10613989B2 (en) 2017-07-14 2020-04-07 Arm Limited Fast address translation for virtual machines
US10565126B2 (en) 2017-07-14 2020-02-18 Arm Limited Method and apparatus for two-layer copy-on-write
US10467159B2 (en) 2017-07-14 2019-11-05 Arm Limited Memory node controller
US10489304B2 (en) 2017-07-14 2019-11-26 Arm Limited Memory address translation
US10534719B2 (en) 2017-07-14 2020-01-14 Arm Limited Memory system for a data processing network
US10592424B2 (en) 2017-07-14 2020-03-17 Arm Limited Range-based memory system
US10884850B2 (en) 2018-07-24 2021-01-05 Arm Limited Fault tolerant memory system

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Also Published As

Publication number Publication date
EP1481323B1 (de) 2007-10-10
HK1072298A1 (en) 2005-08-19
US20030145173A1 (en) 2003-07-31
WO2003065207A3 (en) 2004-05-27
CN1820253A (zh) 2006-08-16
TW200307214A (en) 2003-12-01
WO2003065207A2 (en) 2003-08-07
TWI231914B (en) 2005-05-01
CA2473551A1 (en) 2003-08-07
US7181594B2 (en) 2007-02-20
CA2473551C (en) 2009-01-06
ATE375552T1 (de) 2007-10-15
KR20040017251A (ko) 2004-02-26
AU2003209290A1 (en) 2003-09-02
CN100440151C (zh) 2008-12-03
DE60316774T2 (de) 2008-08-28
EP1481323A2 (de) 2004-12-01
KR100613923B1 (ko) 2006-08-18

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