ATE354830T1 - Netzprozessor, speicherorganisation und verfahren - Google Patents

Netzprozessor, speicherorganisation und verfahren

Info

Publication number
ATE354830T1
ATE354830T1 AT00959157T AT00959157T ATE354830T1 AT E354830 T1 ATE354830 T1 AT E354830T1 AT 00959157 T AT00959157 T AT 00959157T AT 00959157 T AT00959157 T AT 00959157T AT E354830 T1 ATE354830 T1 AT E354830T1
Authority
AT
Austria
Prior art keywords
memory elements
network processor
network
memory organization
processors
Prior art date
Application number
AT00959157T
Other languages
English (en)
Inventor
Brian Mitchell Bass
Jean Louis Calvignac
Marco C Heddes
Piyush Chunilal Patel
Juan Guillermo Revilla
Michael Steven Siegel
Fabrice Jean Verplanken
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE354830T1 publication Critical patent/ATE354830T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Saccharide Compounds (AREA)
AT00959157T 1999-08-27 2000-08-24 Netzprozessor, speicherorganisation und verfahren ATE354830T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/384,744 US6460120B1 (en) 1999-08-27 1999-08-27 Network processor, memory organization and methods

Publications (1)

Publication Number Publication Date
ATE354830T1 true ATE354830T1 (de) 2007-03-15

Family

ID=23518576

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00959157T ATE354830T1 (de) 1999-08-27 2000-08-24 Netzprozessor, speicherorganisation und verfahren

Country Status (8)

Country Link
US (1) US6460120B1 (de)
EP (1) EP1208447B1 (de)
JP (1) JP3832816B2 (de)
KR (1) KR100468800B1 (de)
CN (1) CN1204509C (de)
AT (1) ATE354830T1 (de)
DE (1) DE60033529T2 (de)
WO (1) WO2001016779A1 (de)

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Also Published As

Publication number Publication date
KR20020024332A (ko) 2002-03-29
US20020099855A1 (en) 2002-07-25
EP1208447A1 (de) 2002-05-29
JP2003508851A (ja) 2003-03-04
DE60033529T2 (de) 2007-11-15
KR100468800B1 (ko) 2005-02-02
EP1208447A4 (de) 2004-10-20
JP3832816B2 (ja) 2006-10-11
CN1204509C (zh) 2005-06-01
EP1208447B1 (de) 2007-02-21
CN1369074A (zh) 2002-09-11
DE60033529D1 (de) 2007-04-05
US6460120B1 (en) 2002-10-01
WO2001016779A1 (en) 2001-03-08

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