DE60307798D1 - Arbitrierung von gemeinsamen Speicher - Google Patents

Arbitrierung von gemeinsamen Speicher

Info

Publication number
DE60307798D1
DE60307798D1 DE60307798T DE60307798T DE60307798D1 DE 60307798 D1 DE60307798 D1 DE 60307798D1 DE 60307798 T DE60307798 T DE 60307798T DE 60307798 T DE60307798 T DE 60307798T DE 60307798 D1 DE60307798 D1 DE 60307798D1
Authority
DE
Germany
Prior art keywords
arbitration
shared memory
shared
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60307798T
Other languages
English (en)
Other versions
DE60307798T2 (de
Inventor
Thomas Henkel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verigy Singapore Pte Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE60307798D1 publication Critical patent/DE60307798D1/de
Application granted granted Critical
Publication of DE60307798T2 publication Critical patent/DE60307798T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
DE60307798T 2003-05-30 2003-05-30 Arbitrierung von gemeinsamen Speicher Expired - Lifetime DE60307798T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03101577A EP1482412B1 (de) 2003-05-30 2003-05-30 Arbitrierung von gemeinsamen Speicher

Publications (2)

Publication Number Publication Date
DE60307798D1 true DE60307798D1 (de) 2006-10-05
DE60307798T2 DE60307798T2 (de) 2006-12-14

Family

ID=33104179

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60307798T Expired - Lifetime DE60307798T2 (de) 2003-05-30 2003-05-30 Arbitrierung von gemeinsamen Speicher

Country Status (4)

Country Link
US (1) US7216182B2 (de)
EP (1) EP1482412B1 (de)
JP (1) JP2004362567A (de)
DE (1) DE60307798T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7657672B2 (en) * 2004-01-30 2010-02-02 Telefonaktiebolaget L M Ericsson (Publ) Packet scheduling for data stream transmission
JP4012167B2 (ja) * 2004-03-31 2007-11-21 株式会社東芝 無線通信システム
JP4181093B2 (ja) * 2004-07-16 2008-11-12 株式会社東芝 無線通信システム
JP4275085B2 (ja) * 2005-02-17 2009-06-10 株式会社ソニー・コンピュータエンタテインメント 情報処理装置、情報処理方法、およびデータストリーム生成方法
JP4847036B2 (ja) * 2005-03-30 2011-12-28 キヤノン株式会社 バスアクセスを調停する制御装置およびデータ処理装置の制御方法
US20080059672A1 (en) * 2006-08-30 2008-03-06 Irish John D Methods and Apparatus for Scheduling Prioritized Commands on a Bus
US8307180B2 (en) 2008-02-28 2012-11-06 Nokia Corporation Extended utilization area for a memory device
JP4752882B2 (ja) * 2008-07-24 2011-08-17 ソニー株式会社 メモリアクセスシステム、メモリ制御装置、メモリ制御方法、および、プログラム
WO2010085256A1 (en) * 2009-01-23 2010-07-29 Hewlett-Packard Development Company, L.P. System and methods for allocating shared storage resources
US8713248B2 (en) * 2009-06-02 2014-04-29 Nokia Corporation Memory device and method for dynamic random access memory having serial interface and integral instruction buffer
WO2013098463A1 (en) 2011-12-29 2013-07-04 Nokia Corporation Method for erasing data entity in memory module
US10536565B2 (en) * 2013-03-14 2020-01-14 International Business Machines Corporation Efficient centralized stream initiation and retry control
JP6146128B2 (ja) * 2013-05-20 2017-06-14 ヤマハ株式会社 データ処理装置
WO2015089488A1 (en) 2013-12-12 2015-06-18 Memory Technologies Llc Channel optimized storage modules
JP5911548B1 (ja) 2014-10-23 2016-04-27 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 共有メモリへのアクセス要求をスケジューリングするための装置、方法およびコンピュータプログラム
US10048963B2 (en) 2016-05-23 2018-08-14 International Business Machines Corporation Executing system call vectored instructions in a multi-slice processor
FR3057970B1 (fr) * 2016-10-26 2019-12-13 Zodiac Aero Electric Architecture de communication pour l'echange de donnees entre des unites de traitement
JP2022057224A (ja) 2020-09-30 2022-04-11 株式会社デンソー 共用ストレージ管理装置及び共用ストレージ管理方法
JP2022163404A (ja) * 2021-04-14 2022-10-26 キヤノン株式会社 メモリ制御回路、情報処理システム及びメモリ制御方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117486A (en) * 1989-04-21 1992-05-26 International Business Machines Corp. Buffer for packetizing block of data with different sizes and rates received from first processor before transferring to second processor
CA2080608A1 (en) * 1992-01-02 1993-07-03 Nader Amini Bus control logic for computer system having dual bus architecture
US5530838A (en) * 1993-06-10 1996-06-25 Ricoh Company, Ltd. Method and apparatus for controlling access to memory which is common to plural, priority-ordered central processing units and which is indirectly accessible via a transfer control unit
US5630096A (en) * 1995-05-10 1997-05-13 Microunity Systems Engineering, Inc. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order
US5809538A (en) * 1996-02-07 1998-09-15 General Instrument Corporation DRAM arbiter for video decoder
US5905876A (en) * 1996-12-16 1999-05-18 Intel Corporation Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
US5950229A (en) * 1997-03-12 1999-09-07 Micron Electronics, Inc. System for accelerating memory bandwidth
US6092158A (en) * 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams
US6088772A (en) * 1997-06-13 2000-07-11 Intel Corporation Method and apparatus for improving system performance when reordering commands
US6442628B1 (en) * 1998-05-01 2002-08-27 Adaptec, Inc. Method and system for automatically determining maximum data throughput over a bus
US20020046251A1 (en) * 2001-03-09 2002-04-18 Datacube, Inc. Streaming memory controller
US6622272B1 (en) * 2000-03-10 2003-09-16 Teradyne, Inc. Automatic test equipment methods and apparatus for interfacing with an external device
US6901500B1 (en) * 2000-07-28 2005-05-31 Silicon Graphics, Inc. Method and apparatus for prefetching information and storing the information in a stream buffer
JP2004280926A (ja) * 2003-03-14 2004-10-07 Renesas Technology Corp 半導体記憶装置

Also Published As

Publication number Publication date
US7216182B2 (en) 2007-05-08
EP1482412A1 (de) 2004-12-01
JP2004362567A (ja) 2004-12-24
DE60307798T2 (de) 2006-12-14
US20040243900A1 (en) 2004-12-02
EP1482412B1 (de) 2006-08-23

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: VERIGY (SINGAPORE) PTE. LTD., SINGAPORE, SG

8364 No opposition during term of opposition
R082 Change of representative

Ref document number: 1482412

Country of ref document: EP

Representative=s name: SCHOPPE, ZIMMERMANN, STOECKELER, ZINKLER & PARTNER