DE60232932D1 - Verfahren und Vorrichtung zum Korrigieren der Vorhersage der höchstwertigen Eins - Google Patents
Verfahren und Vorrichtung zum Korrigieren der Vorhersage der höchstwertigen EinsInfo
- Publication number
- DE60232932D1 DE60232932D1 DE60232932T DE60232932T DE60232932D1 DE 60232932 D1 DE60232932 D1 DE 60232932D1 DE 60232932 T DE60232932 T DE 60232932T DE 60232932 T DE60232932 T DE 60232932T DE 60232932 D1 DE60232932 D1 DE 60232932D1
- Authority
- DE
- Germany
- Prior art keywords
- prediction
- correcting
- significant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
- G06F7/485—Adding; Subtracting
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Nonlinear Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/849,052 US6988115B2 (en) | 2001-05-04 | 2001-05-04 | Method and apparatus to correct leading one prediction |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60232932D1 true DE60232932D1 (de) | 2009-08-27 |
Family
ID=25304948
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60232932T Expired - Lifetime DE60232932D1 (de) | 2001-05-04 | 2002-05-01 | Verfahren und Vorrichtung zum Korrigieren der Vorhersage der höchstwertigen Eins |
Country Status (3)
Country | Link |
---|---|
US (2) | US6988115B2 (de) |
EP (1) | EP1255188B1 (de) |
DE (1) | DE60232932D1 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6988115B2 (en) | 2001-05-04 | 2006-01-17 | Broadcom Corporation | Method and apparatus to correct leading one prediction |
US7707236B2 (en) * | 2004-08-13 | 2010-04-27 | Analog Devices, Inc. | Methods and apparatus for an efficient floating point ALU |
US20070038693A1 (en) * | 2005-08-10 | 2007-02-15 | Christian Jacobi | Method and Processor for Performing a Floating-Point Instruction Within a Processor |
US7668892B2 (en) | 2005-08-25 | 2010-02-23 | Arm Limited | Data processing apparatus and method for normalizing a data value |
US8326903B2 (en) * | 2008-01-04 | 2012-12-04 | International Business Machines Corporation | System and method for improved vector analysis |
US9830129B2 (en) * | 2013-11-21 | 2017-11-28 | Samsung Electronics Co., Ltd. | High performance floating-point adder with full in-line denormal/subnormal support |
US10089073B2 (en) * | 2015-01-30 | 2018-10-02 | Huawei Technologies Co., Ltd. | Method and apparatus for converting from integer to floating point representation |
JP6871513B2 (ja) * | 2017-05-22 | 2021-05-12 | 富士通株式会社 | 演算器及び演算器の制御方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922446A (en) | 1988-04-01 | 1990-05-01 | Digital Equipment Corporation | Apparatus and method for floating point normalization prediction |
JPH05241792A (ja) | 1992-02-27 | 1993-09-21 | Nec Corp | 浮動小数点加減算方式および装置 |
EP0663635A1 (de) | 1993-12-15 | 1995-07-19 | Firma Erika Köchler | Schneller serieller Vergleicher |
US5684729A (en) | 1994-09-19 | 1997-11-04 | Hitachi, Ltd. | Floating-point addition/substraction processing apparatus and method thereof |
US5867407A (en) | 1995-06-30 | 1999-02-02 | Digital Equipment Corporation | Normalization shift prediction independent of operand substraction |
KR970016936A (ko) | 1995-09-06 | 1997-04-28 | 엘리 와이스 | 최상위 디지트를 결정하는 장치 및 방법 |
US5633819A (en) * | 1995-10-24 | 1997-05-27 | Exponential Technology, Inc. | Inexact leading-one/leading-zero prediction integrated with a floating-point adder |
US5881217A (en) * | 1996-11-27 | 1999-03-09 | Hewlett-Packard Company | Input comparison circuitry and method for a programmable state machine |
JP3544846B2 (ja) * | 1997-02-13 | 2004-07-21 | 株式会社東芝 | 論理回路及び浮動小数点演算装置 |
US5957997A (en) | 1997-04-25 | 1999-09-28 | International Business Machines Corporation | Efficient floating point normalization mechanism |
US6085208A (en) | 1997-10-23 | 2000-07-04 | Advanced Micro Devices, Inc. | Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit |
US5974432A (en) | 1997-12-05 | 1999-10-26 | Advanced Micro Devices, Inc. | On-the-fly one-hot encoding of leading zero count |
US6571267B1 (en) * | 1999-03-10 | 2003-05-27 | Kabushiki Kaisha Toshiba | Floating point addition/subtraction execution unit |
US6405232B1 (en) * | 1999-08-19 | 2002-06-11 | National Semiconductor Corporation | Leading bit prediction with in-parallel correction |
US6499044B1 (en) * | 1999-11-12 | 2002-12-24 | Jeffrey S. Brooks | Leading zero/one anticipator for floating point |
US6594679B1 (en) * | 2000-03-20 | 2003-07-15 | International Business Machines Corporation | Leading-zero anticipator having an independent sign bit determination module |
US6988115B2 (en) | 2001-05-04 | 2006-01-17 | Broadcom Corporation | Method and apparatus to correct leading one prediction |
-
2001
- 2001-05-04 US US09/849,052 patent/US6988115B2/en not_active Expired - Fee Related
-
2002
- 2002-05-01 EP EP02253078A patent/EP1255188B1/de not_active Expired - Lifetime
- 2002-05-01 DE DE60232932T patent/DE60232932D1/de not_active Expired - Lifetime
-
2005
- 2005-06-07 US US11/146,994 patent/US20050223055A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US6988115B2 (en) | 2006-01-17 |
US20020165887A1 (en) | 2002-11-07 |
EP1255188A2 (de) | 2002-11-06 |
EP1255188B1 (de) | 2009-07-15 |
US20050223055A1 (en) | 2005-10-06 |
EP1255188A3 (de) | 2005-03-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |