DE60225201D1 - Speicherverwaltung für einen gemeinsamen Speicher - Google Patents

Speicherverwaltung für einen gemeinsamen Speicher

Info

Publication number
DE60225201D1
DE60225201D1 DE60225201T DE60225201T DE60225201D1 DE 60225201 D1 DE60225201 D1 DE 60225201D1 DE 60225201 T DE60225201 T DE 60225201T DE 60225201 T DE60225201 T DE 60225201T DE 60225201 D1 DE60225201 D1 DE 60225201D1
Authority
DE
Germany
Prior art keywords
memory
management
shared
shared memory
memory management
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60225201T
Other languages
German (de)
English (en)
Inventor
Barry J Oldfield
Robert A Rust
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE60225201D1 publication Critical patent/DE60225201D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
DE60225201T 2001-03-14 2002-03-07 Speicherverwaltung für einen gemeinsamen Speicher Expired - Lifetime DE60225201D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/808,711 US6799254B2 (en) 2001-03-14 2001-03-14 Memory manager for a common memory

Publications (1)

Publication Number Publication Date
DE60225201D1 true DE60225201D1 (de) 2008-04-10

Family

ID=25199497

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60225201T Expired - Lifetime DE60225201D1 (de) 2001-03-14 2002-03-07 Speicherverwaltung für einen gemeinsamen Speicher

Country Status (4)

Country Link
US (2) US6799254B2 (https=)
EP (1) EP1241580B1 (https=)
JP (1) JP4034969B2 (https=)
DE (1) DE60225201D1 (https=)

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US7272848B1 (en) 2001-02-13 2007-09-18 Network Appliance, Inc. Method for device security in a heterogeneous storage network environment
JP2003114825A (ja) * 2001-10-04 2003-04-18 Hitachi Ltd メモリ制御方法、その制御方法を用いたメモリ制御回路、及びそのメモリ制御回路を搭載する集積回路
US8966081B1 (en) 2002-02-13 2015-02-24 Netapp, Inc. Method for device security in a heterogeneous storage network environment
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US7043582B2 (en) * 2002-09-06 2006-05-09 Intel Corporation Self-nesting interrupts
US6996645B1 (en) * 2002-12-27 2006-02-07 Unisys Corporation Method and apparatus for spawning multiple requests from a single entry of a queue
US7546475B2 (en) * 2003-05-13 2009-06-09 Hewlett-Packard Development Company, L.P. Power-aware adaptation in a data center
TWI256555B (en) * 2003-12-12 2006-06-11 Via Tech Inc An apparatus and a method of request priority queue arbitration
US7302546B2 (en) 2004-01-09 2007-11-27 International Business Machines Corporation Method, system, and article of manufacture for reserving memory
JP4624715B2 (ja) * 2004-05-13 2011-02-02 ルネサスエレクトロニクス株式会社 システムｌｓｉ
JP2005339299A (ja) * 2004-05-28 2005-12-08 Hitachi Ltd ストレージ装置のキャッシュ制御方法
US7417637B1 (en) * 2004-09-01 2008-08-26 Nvidia Corporation Fairly arbitrating between clients
US20060064535A1 (en) * 2004-09-22 2006-03-23 Walker Robert M Efficient multi-bank memory queuing system
US8990377B2 (en) * 2004-12-06 2015-03-24 International Business Machines Corporation Method to effectively collect data from systems that consists of dynamic sub-systems
US7713330B2 (en) * 2004-12-22 2010-05-11 Oreck Holdings, Llc Tower ionizer air cleaner
US7631132B1 (en) * 2004-12-27 2009-12-08 Unisys Corporation Method and apparatus for prioritized transaction queuing
US7356631B2 (en) * 2005-01-21 2008-04-08 Himax Technologies, Inc. Apparatus and method for scheduling requests to source device in a memory access system
US7543119B2 (en) * 2005-02-10 2009-06-02 Richard Edward Hessel Vector processor
US7673111B2 (en) 2005-12-23 2010-03-02 Intel Corporation Memory system with both single and consolidated commands
US20070156955A1 (en) * 2005-12-30 2007-07-05 Royer Robert J Jr Method and apparatus for queuing disk drive access requests
KR20070108432A (ko) * 2006-01-23 2007-11-12 엘지전자 주식회사 장치관리 스케줄링 방법
JP4142068B2 (ja) 2006-06-16 2008-08-27 株式会社ソニー・コンピュータエンタテインメント 情報処理装置およびアクセス制御方法
US7555621B1 (en) * 2006-08-01 2009-06-30 Kaspersky Lab, Zao Disk access antiblocking system and method
US20080282245A1 (en) * 2007-05-08 2008-11-13 International Business Machines Corporation Media Operational Queue Management in Storage Systems
JP4353990B2 (ja) * 2007-05-18 2009-10-28 株式会社半導体理工学研究センター マルチプロセッサ制御装置
TWI352931B (en) * 2007-06-20 2011-11-21 Ind Tech Res Inst Resource management device and method
US8341314B2 (en) * 2009-06-30 2012-12-25 Hewlett-Packard Development Company, L.P. Managing I/O request in storage system
US8639887B2 (en) 2010-06-23 2014-01-28 International Business Machines Corporation Dynamically altering a pipeline controller mode based on resource availability
US8635409B2 (en) 2010-06-23 2014-01-21 International Business Machines Corporation Dynamic mode transitions for cache instructions
US9104491B2 (en) * 2012-02-21 2015-08-11 Disney Enterprises, Inc. Batch scheduler management of speculative and non-speculative tasks based on conditions of tasks and compute resources
US20150019731A1 (en) * 2012-04-23 2015-01-15 Google Inc. Fair Hierarchical Arbitration Of a Shared Resource With Varying Traffic Intensity

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US5253352A (en) * 1989-11-13 1993-10-12 Zenith Data Systems Corporation Method and apparatus for pipelining cache accesses using anticipatory initiation of cache read
US5278984A (en) * 1990-12-19 1994-01-11 Bull Hn Information Systems Inc. Method for managing requests by specifying time intervals for transmitting a minimum number of messages for specific destinations and priority levels
US5588134A (en) * 1992-09-25 1996-12-24 Amdahl Corporation System for establishing priority among selected tasks based on location of tasks and sequence that the tasks were stored whereas task is always stored in location with the lowest available address
US5548795A (en) * 1994-03-28 1996-08-20 Quantum Corporation Method for determining command execution dependencies within command queue reordering process
US5603063A (en) * 1994-06-27 1997-02-11 Quantum Corporation Disk drive command queuing method using two memory devices for storing two types of commands separately first before queuing commands in the second memory device
US6523060B1 (en) * 1995-04-07 2003-02-18 Cisco Technology, Inc. Method and apparatus for the management of queue pointers by multiple processors in a digital communications network
US5796735A (en) * 1995-08-28 1998-08-18 Integrated Device Technology, Inc. System and method for transmission rate control in a segmentation and reassembly (SAR) circuit under ATM protocol
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US5754776A (en) * 1995-12-28 1998-05-19 Intel Corporation Re-prioritizing background data transfers in multipoint conferencing
US5911051A (en) * 1996-03-29 1999-06-08 Intel Corporation High-throughput interconnect allowing bus transactions based on partial access requests
US5748901A (en) * 1996-05-21 1998-05-05 Ramot University Authority Ltd. Flow control algorithm for high speed networks
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US6341301B1 (en) * 1997-01-10 2002-01-22 Lsi Logic Corporation Exclusive multiple queue handling using a common processing algorithm
US6092158A (en) 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams
US6209065B1 (en) * 1997-10-24 2001-03-27 Compaq Computer Corporation Mechanism for optimizing generation of commit-signals in a distributed shared-memory system
GB2332289A (en) * 1997-12-11 1999-06-16 Ibm Handling processor-intensive data processing operations
US6279087B1 (en) * 1997-12-22 2001-08-21 Compaq Computer Corporation System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations
US5948081A (en) 1997-12-22 1999-09-07 Compaq Computer Corporation System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed
US6240492B1 (en) * 1998-05-22 2001-05-29 International Business Machines Corporation Memory interface for functional unit of integrated system allowing access to dedicated memory and shared memory, and speculative generation of lookahead fetch requests
US6272584B1 (en) * 1998-09-10 2001-08-07 Compaq Computer Corporation System board with consolidated EEPROM module
US6175889B1 (en) * 1998-10-21 2001-01-16 Compaq Computer Corporation Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having a plurality of physical buses with a single logical bus number
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US6317806B1 (en) * 1999-05-20 2001-11-13 International Business Machines Corporation Static queue and index queue for storing values identifying static queue locations
US6434641B1 (en) * 1999-05-28 2002-08-13 Unisys Corporation System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme
US6633565B1 (en) * 1999-06-29 2003-10-14 3Com Corporation Apparatus for and method of flow switching in a data communications network
US6564304B1 (en) * 2000-09-01 2003-05-13 Ati Technologies Inc. Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching

Also Published As

Publication number Publication date
US6950912B2 (en) 2005-09-27
JP2002278827A (ja) 2002-09-27
JP4034969B2 (ja) 2008-01-16
EP1241580A3 (en) 2003-10-29
EP1241580B1 (en) 2008-02-27
US20020133676A1 (en) 2002-09-19
US6799254B2 (en) 2004-09-28
EP1241580A2 (en) 2002-09-18
US20040243771A1 (en) 2004-12-02

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Legal Events

Date Code Title Description
8332 No legal effect for de