DE60223403D1 - Spreizband-takt tolerante empfänger - Google Patents

Spreizband-takt tolerante empfänger

Info

Publication number
DE60223403D1
DE60223403D1 DE60223403T DE60223403T DE60223403D1 DE 60223403 D1 DE60223403 D1 DE 60223403D1 DE 60223403 T DE60223403 T DE 60223403T DE 60223403 T DE60223403 T DE 60223403T DE 60223403 D1 DE60223403 D1 DE 60223403D1
Authority
DE
Germany
Prior art keywords
data signal
signal
phase
tolerant receiver
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60223403T
Other languages
English (en)
Other versions
DE60223403T2 (de
Inventor
Harry Skinner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60223403D1 publication Critical patent/DE60223403D1/de
Publication of DE60223403T2 publication Critical patent/DE60223403T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
    • H04B15/04—Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2215/00—Reducing interference at the transmission system level
    • H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2215/00—Reducing interference at the transmission system level
    • H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
    • H04B2215/067—Reduction of clock or synthesizer reference frequency harmonics by modulation dispersion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Eye Examination Apparatus (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Cleaning And De-Greasing Of Metallic Materials By Chemical Methods (AREA)
  • Burglar Alarm Systems (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
DE60223403T 2001-12-26 2002-12-19 Spreizband-takt tolerante empfänger Expired - Lifetime DE60223403T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US34398 2001-12-26
US10/034,398 US6937679B2 (en) 2001-12-26 2001-12-26 Spread spectrum clocking tolerant receivers
PCT/US2002/041153 WO2003058874A1 (en) 2001-12-26 2002-12-19 Spread spectrum clocking tolerant receivers

Publications (2)

Publication Number Publication Date
DE60223403D1 true DE60223403D1 (de) 2007-12-20
DE60223403T2 DE60223403T2 (de) 2008-09-04

Family

ID=21876139

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60223403T Expired - Lifetime DE60223403T2 (de) 2001-12-26 2002-12-19 Spreizband-takt tolerante empfänger

Country Status (8)

Country Link
US (1) US6937679B2 (de)
EP (1) EP1459473B1 (de)
KR (1) KR100693985B1 (de)
CN (1) CN100334828C (de)
AT (1) ATE377879T1 (de)
AU (1) AU2002360740A1 (de)
DE (1) DE60223403T2 (de)
WO (1) WO2003058874A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7209525B2 (en) * 2002-11-18 2007-04-24 Agere Systems Inc. Clock and data recovery with extended integration cycles
US7315595B2 (en) * 2003-12-22 2008-01-01 International Business Machines Corporation Methods and arrangements for link power reduction
US7738617B1 (en) 2004-09-29 2010-06-15 Pmc-Sierra, Inc. Clock and data recovery locking technique for large frequency offsets
US7558357B1 (en) 2004-10-26 2009-07-07 Pmc-Sierra, Inc. Systems and methods for reducing frequency-offset induced jitter
US7664204B1 (en) * 2005-03-10 2010-02-16 Marvell International Ltd. Adaptive timing using clock recovery
JP2007151099A (ja) * 2005-10-28 2007-06-14 Seiko Epson Corp 無線通信装置
US8483703B2 (en) * 2005-11-14 2013-07-09 Motorola Solutions, Inc. Method and apparatus for locating a transceiver
US20070159744A1 (en) * 2006-01-06 2007-07-12 Ramen Dutta High voltage pin for low voltage process
JP2008011173A (ja) * 2006-06-29 2008-01-17 Nippon Telegr & Teleph Corp <Ntt> Ｃｄｒ回路
KR101088065B1 (ko) 2006-06-29 2011-11-30 니폰덴신뎅와 가부시키가이샤 Ｃｄｒ 회로
KR20090082208A (ko) 2006-10-06 2009-07-29 램버스 인코포레이티드 주파수의 도함수의 구분적 추정치를 사용하는 클럭 및 데이터 복구
GB2453732B (en) * 2007-10-16 2012-03-07 Virtensys Ltd Data switch
US8169369B2 (en) * 2008-12-15 2012-05-01 Motorola Solutions, Inc. Method and device for generating a location signal
KR101642833B1 (ko) * 2010-02-05 2016-07-26 삼성전자주식회사 클럭 임베디드 인터페이스 방법, 그 방법을 이용하는 송수신기 및 디스플레이 장치
JP6421515B2 (ja) * 2014-09-25 2018-11-14 富士通株式会社 信号再生回路および信号再生方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU4971096A (en) 1995-03-08 1996-09-23 Intel Corporation Frequency modulated clock for reduced radiation
JP3403849B2 (ja) * 1995-03-17 2003-05-06 富士通株式会社 多重無線装置の受信部に設けられるクロック位相検出回路及びクロック再生回路
US5696800A (en) 1995-03-22 1997-12-09 Intel Corporation Dual tracking differential manchester decoder and clock recovery circuit
JP3120833B2 (ja) 1997-05-20 2000-12-25 日本電気株式会社 バースト信号復調装置
US6236697B1 (en) * 1998-05-28 2001-05-22 Integrated Device Technology, Inc. Clock recovery for multiple frequency input data
US6347128B1 (en) * 1998-07-20 2002-02-12 Lucent Technologies Inc. Self-aligned clock recovery circuit with proportional phase detector

Also Published As

Publication number Publication date
KR100693985B1 (ko) 2007-03-13
WO2003058874A1 (en) 2003-07-17
DE60223403T2 (de) 2008-09-04
US20030118137A1 (en) 2003-06-26
CN100334828C (zh) 2007-08-29
US6937679B2 (en) 2005-08-30
AU2002360740A1 (en) 2003-07-24
KR20040074103A (ko) 2004-08-21
ATE377879T1 (de) 2007-11-15
EP1459473B1 (de) 2007-11-07
EP1459473A1 (de) 2004-09-22
CN1608360A (zh) 2005-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition