DE60222175D1 - Bildverarbeitungsvorrichtung und verfahren dafür - Google Patents

Bildverarbeitungsvorrichtung und verfahren dafür

Info

Publication number
DE60222175D1
DE60222175D1 DE60222175T DE60222175T DE60222175D1 DE 60222175 D1 DE60222175 D1 DE 60222175D1 DE 60222175 T DE60222175 T DE 60222175T DE 60222175 T DE60222175 T DE 60222175T DE 60222175 D1 DE60222175 D1 DE 60222175D1
Authority
DE
Germany
Prior art keywords
image processing
processing device
method therefor
therefor
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60222175T
Other languages
English (en)
Other versions
DE60222175T2 (de
Inventor
Yuji Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE60222175D1 publication Critical patent/DE60222175D1/de
Application granted granted Critical
Publication of DE60222175T2 publication Critical patent/DE60222175T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/04—Texture mapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00—Indexing scheme for image generation or computer graphics
    • G06T2210/52—Parallel processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y10S707/99932—Access augmentation or optimizing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Graphics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)
DE60222175T 2001-12-12 2002-12-11 Bildverarbeitungsvorrichtung und dazugehöriges verfahren Expired - Lifetime DE60222175T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001379350A JP3840966B2 (ja) 2001-12-12 2001-12-12 画像処理装置およびその方法
JP2001379350 2001-12-12
PCT/JP2002/012965 WO2003050759A1 (fr) 2001-12-12 2002-12-11 Appareil de traitement d'images et procede associe

Publications (2)

Publication Number Publication Date
DE60222175D1 true DE60222175D1 (de) 2007-10-11
DE60222175T2 DE60222175T2 (de) 2008-05-21

Family

ID=19186758

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60222175T Expired - Lifetime DE60222175T2 (de) 2001-12-12 2002-12-11 Bildverarbeitungsvorrichtung und dazugehöriges verfahren

Country Status (7)

Country Link
US (1) US7333115B2 (de)
EP (1) EP1460581B1 (de)
JP (1) JP3840966B2 (de)
KR (1) KR100857657B1 (de)
CN (1) CN1297939C (de)
DE (1) DE60222175T2 (de)
WO (1) WO2003050759A1 (de)

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US6937244B2 (en) * 2003-09-23 2005-08-30 Zhou (Mike) Hong Apparatus and method for reducing the memory traffic of a graphics rendering system
JP4030519B2 (ja) * 2004-04-15 2008-01-09 株式会社東芝 画像処理装置および画像処理システム
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US7750914B2 (en) 2004-08-26 2010-07-06 Intel Corporation Subdividing geometry images in graphics hardware
KR100868396B1 (ko) * 2004-08-26 2008-11-11 인텔 코오퍼레이션 기하 이미지 분할을 위한 그래픽 처리 시스템 및 방법
US8624906B2 (en) 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
WO2006055546A2 (en) * 2004-11-15 2006-05-26 Nvidia Corporation A video processor having a scalar component controlling a vector component to implement video processing
US8725990B1 (en) 2004-11-15 2014-05-13 Nvidia Corporation Configurable SIMD engine with high, low and mixed precision modes
JP2006202211A (ja) * 2005-01-24 2006-08-03 Fujitsu Ltd 画像描画装置および画像描画方法
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US8232991B1 (en) * 2006-11-03 2012-07-31 Nvidia Corporation Z-test result reconciliation with multiple partitions
US8265169B2 (en) 2006-12-29 2012-09-11 Intel Corporation Video block memory read request translation and tagging
CN100533485C (zh) * 2007-01-17 2009-08-26 威盛电子股份有限公司 影像描绘方法
US8683126B2 (en) 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8923385B2 (en) 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8681861B2 (en) 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
EP2294571A4 (de) * 2008-05-30 2014-04-23 Advanced Micro Devices Inc Schattiererkomplex mit einem verteilten level-one-cache-system und zentralisiertem level-two-cache
US8489851B2 (en) 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
US8314949B2 (en) * 2008-12-23 2012-11-20 Infoprint Solutions Company Llc Distributed global object cache
US7924860B1 (en) * 2008-12-23 2011-04-12 Juniper Networks, Inc. Maintaining data unit order in a network switching device
JP5404433B2 (ja) * 2010-01-08 2014-01-29 株式会社東芝 マルチコアシステム
CN103080981B (zh) * 2010-08-27 2016-03-02 矽锂铬艺术有限公司 选择纹理映射水平的方法及利用该方法的材质贴图系统
AU2010241218B2 (en) * 2010-11-03 2013-10-31 Canon Kabushiki Kaisha Method, apparatus and system for associating an intermediate fill with a plurality of objects
US9552206B2 (en) * 2010-11-18 2017-01-24 Texas Instruments Incorporated Integrated circuit with control node circuitry and processing circuitry
CN102542525B (zh) * 2010-12-13 2014-02-12 联想(北京)有限公司 一种信息处理设备以及信息处理方法
US20130007369A1 (en) * 2011-06-29 2013-01-03 International Business Machines Corporation Transparent Cache for Mobile Users
CN103034465B (zh) * 2011-09-29 2016-04-27 腾讯科技（深圳）有限公司 图像浏览方法及浏览系统
US10055810B2 (en) * 2016-03-04 2018-08-21 Samsung Electronics Co., Ltd. Cache architecture for efficiently accessing texture data using buffers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882357A (ja) * 1981-11-11 1983-05-17 Hitachi Ltd プロセツサ間通信方式
JPH0348979A (ja) * 1989-07-17 1991-03-01 Nec Corp 並列画像処理装置
KR0140674B1 (ko) * 1993-04-12 1998-06-15 모리시다 요이치 영상신호처리장치 및 처리방법
US5832534A (en) 1994-01-04 1998-11-03 Intel Corporation Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
CN1081368C (zh) * 1997-06-27 2002-03-20 清华大学 实现邻域图象数据并行存取的方法及邻域图象帧存储体
US6662173B1 (en) * 1998-12-31 2003-12-09 Intel Corporation Access control of a resource shared between components
JP2001273191A (ja) * 2000-03-24 2001-10-05 Seiko Epson Corp コンピュータシステム
US6904499B2 (en) * 2001-03-30 2005-06-07 Intel Corporation Controlling cache memory in external chipset using processor

Also Published As

Publication number Publication date
US20040111489A1 (en) 2004-06-10
EP1460581B1 (de) 2007-08-29
CN1491401A (zh) 2004-04-21
CN1297939C (zh) 2007-01-31
WO2003050759A1 (fr) 2003-06-19
KR20040080920A (ko) 2004-09-20
JP3840966B2 (ja) 2006-11-01
US7333115B2 (en) 2008-02-19
DE60222175T2 (de) 2008-05-21
KR100857657B1 (ko) 2008-09-08
EP1460581A4 (de) 2006-07-12
EP1460581A1 (de) 2004-09-22
JP2003178294A (ja) 2003-06-27

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Legal Events

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8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)