DE60210312D1 - I/o-vermittlungsknoten für verbindungen in einem multiprozessorrechnersystem - Google Patents

I/o-vermittlungsknoten für verbindungen in einem multiprozessorrechnersystem

Info

Publication number
DE60210312D1
DE60210312D1 DE60210312T DE60210312T DE60210312D1 DE 60210312 D1 DE60210312 D1 DE 60210312D1 DE 60210312 T DE60210312 T DE 60210312T DE 60210312 T DE60210312 T DE 60210312T DE 60210312 D1 DE60210312 D1 DE 60210312D1
Authority
DE
Germany
Prior art keywords
connections
computer system
communication nodes
multiprocessor computer
multiprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60210312T
Other languages
English (en)
Other versions
DE60210312T2 (de
Inventor
E Gulick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE60210312D1 publication Critical patent/DE60210312D1/de
Publication of DE60210312T2 publication Critical patent/DE60210312T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE60210312T 2001-11-30 2002-09-12 I/o-vermittlungsknoten für verbindungen in einem multiprozessorrechnersystem Expired - Lifetime DE60210312T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/998,758 US6836813B1 (en) 2001-11-30 2001-11-30 Switching I/O node for connection in a multiprocessor computer system
US998758 2001-11-30
PCT/US2002/028985 WO2003048951A1 (en) 2001-11-30 2002-09-12 A switching i/o node for connection in a multiprocessor computer system

Publications (2)

Publication Number Publication Date
DE60210312D1 true DE60210312D1 (de) 2006-05-18
DE60210312T2 DE60210312T2 (de) 2006-12-14

Family

ID=25545535

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60210312T Expired - Lifetime DE60210312T2 (de) 2001-11-30 2002-09-12 I/o-vermittlungsknoten für verbindungen in einem multiprozessorrechnersystem

Country Status (9)

Country Link
US (1) US6836813B1 (de)
EP (1) EP1449100B1 (de)
JP (1) JP4290556B2 (de)
KR (1) KR100950101B1 (de)
CN (1) CN1320469C (de)
AU (1) AU2002336494A1 (de)
DE (1) DE60210312T2 (de)
TW (1) TWI236251B (de)
WO (1) WO2003048951A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7640843B2 (en) 2003-01-24 2010-01-05 Kraft Foods R & D, Inc. Cartridge and method for the preparation of beverages
CN1332334C (zh) * 2004-01-17 2007-08-15 中国科学院计算技术研究所 一种多处理机通信装置及其通信方法
US20050262391A1 (en) * 2004-05-10 2005-11-24 Prashant Sethi I/O configuration messaging within a link-based computing system
US20050286526A1 (en) * 2004-06-25 2005-12-29 Sood Sanjeev H Optimized algorithm for stream re-assembly
US20060004933A1 (en) * 2004-06-30 2006-01-05 Sujoy Sen Network interface controller signaling of connection event
US7461173B2 (en) * 2004-06-30 2008-12-02 Intel Corporation Distributing timers across processors
US20060031474A1 (en) * 2004-07-19 2006-02-09 Linden Cornett Maintaining reachability measures
US7907298B2 (en) * 2004-10-15 2011-03-15 Fujifilm Dimatix, Inc. Data pump for printing
JP4711709B2 (ja) * 2005-03-18 2011-06-29 富士通株式会社 パーティション割り振り方法及びコンピュータシステム
CN100447714C (zh) * 2005-11-04 2008-12-31 英业达股份有限公司 多任务式计算机周边装置联机切换接口
US7370135B2 (en) 2005-11-21 2008-05-06 Intel Corporation Band configuration agent for link based computing system
CN100454277C (zh) * 2006-01-27 2009-01-21 威盛电子股份有限公司 支持快速外围互连装置的计算机系统及相关方法
US7647476B2 (en) * 2006-03-14 2010-01-12 Intel Corporation Common analog interface for multiple processor cores
CN101501660B (zh) 2006-08-09 2011-11-16 日本电气株式会社 因特网连接交换机和因特网连接系统
US7853638B2 (en) * 2007-01-26 2010-12-14 International Business Machines Corporation Structure for a flexibly configurable multi central processing unit (CPU) supported hypertransport switching
US7797475B2 (en) * 2007-01-26 2010-09-14 International Business Machines Corporation Flexibly configurable multi central processing unit (CPU) supported hypertransport switching
US7930459B2 (en) * 2007-09-28 2011-04-19 Intel Corporation Coherent input output device
US9442540B2 (en) * 2009-08-28 2016-09-13 Advanced Green Computing Machines-Ip, Limited High density multi node computer with integrated shared resources
JP5482263B2 (ja) * 2010-02-08 2014-05-07 日本電気株式会社 エンドポイント共有システムおよびデータ転送方法
US9176913B2 (en) 2011-09-07 2015-11-03 Apple Inc. Coherence switch for I/O traffic
US9875204B2 (en) * 2012-05-18 2018-01-23 Dell Products, Lp System and method for providing a processing node with input/output functionality provided by an I/O complex switch
CN104268107B (zh) * 2014-09-05 2017-04-05 中国运载火箭技术研究院 一种箭载计算机处理器与外总线接口余度管理分离的系统
US10387346B2 (en) 2016-05-06 2019-08-20 Quanta Computer Inc. Dynamic PCIE switch reconfiguration mechanism

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5533198A (en) 1992-11-30 1996-07-02 Cray Research, Inc. Direction order priority routing of packets between nodes in a networked system
KR100304063B1 (ko) 1993-08-04 2001-11-22 썬 마이크로시스템즈, 인코포레이티드 2지점간상호접속통신유틸리티
AUPM699394A0 (en) 1994-07-25 1994-08-18 Curtin University Of Technology Link level controlled access to available asynchronous network service
US6175888B1 (en) 1996-04-10 2001-01-16 International Business Machines Corporation Dual host bridge with peer to peer support
US5991824A (en) * 1997-02-06 1999-11-23 Silicon Graphics, Inc. Method and system for simultaneous high bandwidth input output
US6085276A (en) 1997-10-24 2000-07-04 Compaq Computers Corporation Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies
US6424658B1 (en) * 1999-01-29 2002-07-23 Neomagic Corp. Store-and-forward network switch using an embedded DRAM
JP2001014269A (ja) * 1999-06-29 2001-01-19 Toshiba Corp コンピュータシステム
US6668299B1 (en) 1999-09-08 2003-12-23 Mellanox Technologies Ltd. Software interface between a parallel bus and a packet network
WO2001018988A1 (en) 1999-09-08 2001-03-15 Mellanox Technologies Ltd. Bridge between parallel buses over a packet-switched network
US6604161B1 (en) * 1999-09-29 2003-08-05 Silicon Graphics, Inc. Translation of PCI level interrupts into packet based messages for edge event drive microprocessors
JP2001325207A (ja) * 2000-05-17 2001-11-22 Hitachi Ltd キャッシュ内蔵型スイッチおよび計算機システムおよびキャッシュ内蔵型スイッチのスイッチ制御方法

Also Published As

Publication number Publication date
KR100950101B1 (ko) 2010-03-29
WO2003048951A1 (en) 2003-06-12
US6836813B1 (en) 2004-12-28
KR20050027083A (ko) 2005-03-17
JP2005512194A (ja) 2005-04-28
TWI236251B (en) 2005-07-11
CN1592895A (zh) 2005-03-09
JP4290556B2 (ja) 2009-07-08
EP1449100A1 (de) 2004-08-25
DE60210312T2 (de) 2006-12-14
EP1449100B1 (de) 2006-03-29
CN1320469C (zh) 2007-06-06
AU2002336494A1 (en) 2003-06-17

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