DE60034470D1 - Netzwerkstoplogie für ein skalierbares mehrrechnersystem - Google Patents

Netzwerkstoplogie für ein skalierbares mehrrechnersystem

Info

Publication number
DE60034470D1
DE60034470D1 DE60034470T DE60034470T DE60034470D1 DE 60034470 D1 DE60034470 D1 DE 60034470D1 DE 60034470 T DE60034470 T DE 60034470T DE 60034470 T DE60034470 T DE 60034470T DE 60034470 D1 DE60034470 D1 DE 60034470D1
Authority
DE
Germany
Prior art keywords
stopoplogy
network
computer system
scalable multi
scalable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60034470T
Other languages
English (en)
Other versions
DE60034470T2 (de
Inventor
Martin M Deneroff
Gregory M Thorson
Randal S Passint
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Graphics Properties Holdings Inc
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Application granted granted Critical
Publication of DE60034470D1 publication Critical patent/DE60034470D1/de
Publication of DE60034470T2 publication Critical patent/DE60034470T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17312—Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/14—Routing performance; Theoretical aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1001—Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE60034470T 1999-09-29 2000-09-29 Massiv paralleles Datenverarbeitungssystem und skalierbares Verbindungsnetz für ein solches System Expired - Fee Related DE60034470T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US408972 1982-08-17
US09/408,972 US6973559B1 (en) 1999-09-29 1999-09-29 Scalable hypercube multiprocessor network for massive parallel processing
PCT/US2000/027024 WO2001024029A2 (en) 1999-09-29 2000-09-29 Network topology for a scalable multiprocessor system

Publications (2)

Publication Number Publication Date
DE60034470D1 true DE60034470D1 (de) 2007-05-31
DE60034470T2 DE60034470T2 (de) 2008-01-03

Family

ID=23618525

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60034470T Expired - Fee Related DE60034470T2 (de) 1999-09-29 2000-09-29 Massiv paralleles Datenverarbeitungssystem und skalierbares Verbindungsnetz für ein solches System

Country Status (5)

Country Link
US (5) US6973559B1 (de)
EP (1) EP1222557B1 (de)
JP (1) JP4480315B2 (de)
DE (1) DE60034470T2 (de)
WO (1) WO2001024029A2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6973559B1 (en) 1999-09-29 2005-12-06 Silicon Graphics, Inc. Scalable hypercube multiprocessor network for massive parallel processing
US7436775B2 (en) * 2003-07-24 2008-10-14 Alcatel Lucent Software configurable cluster-based router using stock personal computers as cluster nodes
US20050138324A1 (en) * 2003-12-19 2005-06-23 International Business Machines Corporation Processing unit having a dual channel bus architecture
US7486619B2 (en) * 2004-03-04 2009-02-03 International Business Machines Corporation Multidimensional switch network
US9990607B1 (en) * 2006-01-13 2018-06-05 Wensheng Hua Balanced network and method
US7826455B2 (en) * 2007-11-02 2010-11-02 Cisco Technology, Inc. Providing single point-of-presence across multiple processors
US7872990B2 (en) * 2008-04-30 2011-01-18 Microsoft Corporation Multi-level interconnection network
US8001310B2 (en) 2009-03-04 2011-08-16 Hewlett-Packard Development Company, L.P. Scalable computer node having an expansion module that is socket-compatible with a central processing unit
US9479358B2 (en) * 2009-05-13 2016-10-25 International Business Machines Corporation Managing graphics load balancing strategies
US8307116B2 (en) * 2009-06-19 2012-11-06 Board Of Regents Of The University Of Texas System Scalable bus-based on-chip interconnection networks
TWI410087B (zh) * 2010-12-20 2013-09-21 Ind Tech Res Inst 多核心晶片網路
CN103891214B (zh) 2011-10-26 2016-08-24 国际商业机器公司 优化超立方体网络中的数据传输的方法和系统
US9294419B2 (en) * 2013-06-26 2016-03-22 Intel Corporation Scalable multi-layer 2D-mesh routers
JP6337606B2 (ja) 2014-05-15 2018-06-06 富士通株式会社 情報処理装置、経路決定方法及びプログラム
RU2635896C1 (ru) * 2016-07-07 2017-11-16 Акционерное общество "Научно-исследовательский институт вычислительных комплексов им. М.А. Карцева" (АО "НИИВК им. М.А. Карцева") Высокопроизводительная вычислительная платформа на базе процессоров с разнородной архитектурой
US10057334B2 (en) * 2016-11-14 2018-08-21 Futurewei Technologies, Inc. Quad full mesh and dimension driven network architecture
RU2708794C2 (ru) * 2018-05-21 2019-12-11 Общество с ограниченной ответственностью "Центр инженерной физики при МГУ имени М.В. Ломоносова" Вычислительный модуль для многопотоковой обработки цифровых данных и способ обработки с использованием данного модуля
US11750531B2 (en) 2019-01-17 2023-09-05 Ciena Corporation FPGA-based virtual fabric for data center computing

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5113523A (en) * 1985-05-06 1992-05-12 Ncube Corporation High performance computer system
US4860201A (en) * 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
JPS63172362A (ja) 1987-01-12 1988-07-16 Fujitsu Ltd プロセツサ間通信方式
DE3889550T2 (de) 1987-01-12 1994-09-01 Fujitsu Ltd Datenübertragungspufferschaltungen für Datenaustausch.
US5187801A (en) * 1990-04-11 1993-02-16 Thinking Machines Corporation Massively-parallel computer system for generating paths in a binomial lattice
US5133073A (en) * 1990-05-29 1992-07-21 Wavetracer, Inc. Processor array of N-dimensions which is physically reconfigurable into N-1
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5794059A (en) * 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
US5625836A (en) * 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
IE920032A1 (en) * 1991-01-11 1992-07-15 Marconi Gec Ltd Parallel processing apparatus
US5263124A (en) * 1991-02-27 1993-11-16 Neural Systems Corporation Method for producing a binary tree, pattern recognition and binary vector classification method using binary trees, and system for classifying binary vectors
US5471580A (en) * 1991-10-01 1995-11-28 Hitachi, Ltd. Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer
JPH05204876A (ja) 1991-10-01 1993-08-13 Hitachi Ltd 階層型ネットワークおよび階層型ネットワークを用いたマルチプロセッサシステム
IT1260848B (it) * 1993-06-11 1996-04-23 Finmeccanica Spa Sistema a multiprocessore
US5669008A (en) * 1995-05-05 1997-09-16 Silicon Graphics, Inc. Hierarchical fat hypercube architecture for parallel processing systems
US6041358A (en) * 1996-11-12 2000-03-21 Industrial Technology Research Inst. Method for maintaining virtual local area networks with mobile terminals in an ATM network
US6230252B1 (en) * 1997-11-17 2001-05-08 Silicon Graphics, Inc. Hybrid hypercube/torus architecture
US6334177B1 (en) * 1998-12-18 2001-12-25 International Business Machines Corporation Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system
US6973559B1 (en) 1999-09-29 2005-12-06 Silicon Graphics, Inc. Scalable hypercube multiprocessor network for massive parallel processing

Also Published As

Publication number Publication date
JP4480315B2 (ja) 2010-06-16
DE60034470T2 (de) 2008-01-03
US8433816B2 (en) 2013-04-30
US20060282648A1 (en) 2006-12-14
US9514092B2 (en) 2016-12-06
JP2003510720A (ja) 2003-03-18
US6973559B1 (en) 2005-12-06
EP1222557B1 (de) 2007-04-18
EP1222557A2 (de) 2002-07-17
US20130246653A1 (en) 2013-09-19
US20090113172A1 (en) 2009-04-30
US20160337229A1 (en) 2016-11-17
WO2001024029A3 (en) 2001-08-30
WO2001024029A2 (en) 2001-04-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee