DE602008003874D1 - Verfahren und System zur Zuordnung mehrerer Macs zu mehreren Prozessoren - Google Patents

Verfahren und System zur Zuordnung mehrerer Macs zu mehreren Prozessoren

Info

Publication number
DE602008003874D1
DE602008003874D1 DE602008003874T DE602008003874T DE602008003874D1 DE 602008003874 D1 DE602008003874 D1 DE 602008003874D1 DE 602008003874 T DE602008003874 T DE 602008003874T DE 602008003874 T DE602008003874 T DE 602008003874T DE 602008003874 D1 DE602008003874 D1 DE 602008003874D1
Authority
DE
Germany
Prior art keywords
macs
assigning
processors
multiple processors
assigning multiple
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602008003874T
Other languages
English (en)
Inventor
Koby Rosenberg
Avishay Halavy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polycom Inc
Original Assignee
Polycom Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Polycom Inc filed Critical Polycom Inc
Publication of DE602008003874D1 publication Critical patent/DE602008003874D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/355—Application aware switches, e.g. for HTTP
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/40—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2025—Failover techniques using centralised failover control functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Hardware Redundancy (AREA)
DE602008003874T 2007-09-11 2008-08-29 Verfahren und System zur Zuordnung mehrerer Macs zu mehreren Prozessoren Active DE602008003874D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US97141507P 2007-09-11 2007-09-11

Publications (1)

Publication Number Publication Date
DE602008003874D1 true DE602008003874D1 (de) 2011-01-20

Family

ID=39870462

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602008003874T Active DE602008003874D1 (de) 2007-09-11 2008-08-29 Verfahren und System zur Zuordnung mehrerer Macs zu mehreren Prozessoren

Country Status (7)

Country Link
US (1) US7898941B2 (de)
EP (1) EP2037364B1 (de)
JP (1) JP4860677B2 (de)
CN (2) CN101515885B (de)
DE (1) DE602008003874D1 (de)
HK (1) HK1122630A1 (de)
TW (1) TWI383616B (de)

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JP4811489B2 (ja) * 2009-03-27 2011-11-09 日本電気株式会社 サーバシステム、集合型サーバ装置及びｍａｃアドレス管理方法
US20110103391A1 (en) * 2009-10-30 2011-05-05 Smooth-Stone, Inc. C/O Barry Evans System and method for high-performance, low-power data center interconnect fabric
CN102149116B (zh) * 2011-04-02 2015-05-20 迈普通信技术股份有限公司 一种无线个域网协调器的备份方法及装置
IN2015DN04195A (de) * 2012-12-20 2015-10-16 Ericsson Telefon Ab L M
US9146890B1 (en) * 2013-01-25 2015-09-29 Pmc—Sierra Us, Inc. Method and apparatus for mapped I/O routing in an interconnect switch
US9092353B1 (en) 2013-01-29 2015-07-28 Pmc-Sierra Us, Inc. Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system
US9813080B1 (en) 2013-03-05 2017-11-07 Microsemi Solutions (U.S.), Inc. Layer specific LDPC decoder
US10230396B1 (en) 2013-03-05 2019-03-12 Microsemi Solutions (Us), Inc. Method and apparatus for layer-specific LDPC decoding
US9397701B1 (en) 2013-03-11 2016-07-19 Microsemi Storage Solutions (Us), Inc. System and method for lifetime specific LDPC decoding
US9590656B2 (en) 2013-03-15 2017-03-07 Microsemi Storage Solutions (Us), Inc. System and method for higher quality log likelihood ratios in LDPC decoding
US9450610B1 (en) 2013-03-15 2016-09-20 Microsemi Storage Solutions (Us), Inc. High quality log likelihood ratios determined using two-index look-up table
US9454414B2 (en) 2013-03-15 2016-09-27 Microsemi Storage Solutions (Us), Inc. System and method for accumulating soft information in LDPC decoding
US9417804B2 (en) 2014-07-07 2016-08-16 Microsemi Storage Solutions (Us), Inc. System and method for memory block pool wear leveling
US9450916B2 (en) * 2014-08-22 2016-09-20 Honeywell International Inc. Hardware assist for redundant ethernet network
US10332613B1 (en) 2015-05-18 2019-06-25 Microsemi Solutions (Us), Inc. Nonvolatile memory system with retention monitor
US9799405B1 (en) 2015-07-29 2017-10-24 Ip Gem Group, Llc Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction
US9886214B2 (en) 2015-12-11 2018-02-06 Ip Gem Group, Llc Nonvolatile memory system with erase suspend circuit and method for erase suspend management
US9892794B2 (en) 2016-01-04 2018-02-13 Ip Gem Group, Llc Method and apparatus with program suspend using test mode
US9899092B2 (en) 2016-01-27 2018-02-20 Ip Gem Group, Llc Nonvolatile memory system with program step manager and method for program step management
CN106200454B (zh) * 2016-06-21 2019-03-29 沈阳东软医疗系统有限公司 一种多mcu的通信系统及方法
US10157677B2 (en) 2016-07-28 2018-12-18 Ip Gem Group, Llc Background reference positioning and local reference positioning using threshold voltage shift read
US10291263B2 (en) 2016-07-28 2019-05-14 Ip Gem Group, Llc Auto-learning log likelihood ratio
US10236915B2 (en) 2016-07-29 2019-03-19 Microsemi Solutions (U.S.), Inc. Variable T BCH encoding
CN109508491B (zh) * 2018-11-09 2023-05-30 辽宁石油化工大学 一种基于控制器失效的反应釜系统保成本控制器设计方法
US11425771B2 (en) * 2019-11-27 2022-08-23 At&T Intellectual Property I, L.P. Medium access control interface to coordinate multi-site operation for 5G or other next generation wireless network

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Also Published As

Publication number Publication date
EP2037364B1 (de) 2010-12-08
US7898941B2 (en) 2011-03-01
EP2037364A1 (de) 2009-03-18
JP4860677B2 (ja) 2012-01-25
CN101515885A (zh) 2009-08-26
TW200929928A (en) 2009-07-01
TWI383616B (zh) 2013-01-21
CN103002072A (zh) 2013-03-27
CN101515885B (zh) 2012-12-05
JP2009071820A (ja) 2009-04-02
US20090067320A1 (en) 2009-03-12
HK1122630A1 (en) 2009-05-22

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