DE602007014043D1 - Dynamische peripheriefunktionsumabbildung auf externe eingangs-ausgangs-verbindungen einer integrierten schaltungsanordnung - Google Patents

Dynamische peripheriefunktionsumabbildung auf externe eingangs-ausgangs-verbindungen einer integrierten schaltungsanordnung

Info

Publication number
DE602007014043D1
DE602007014043D1 DE602007014043T DE602007014043T DE602007014043D1 DE 602007014043 D1 DE602007014043 D1 DE 602007014043D1 DE 602007014043 T DE602007014043 T DE 602007014043T DE 602007014043 T DE602007014043 T DE 602007014043T DE 602007014043 D1 DE602007014043 D1 DE 602007014043D1
Authority
DE
Germany
Prior art keywords
output
external input
integrated circuit
output connections
mapped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007014043T
Other languages
English (en)
Inventor
Igor Wojewoda
Brian Boles
Steve Bradley
Gaurang Kavaiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of DE602007014043D1 publication Critical patent/DE602007014043D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE602007014043T 2006-06-02 2007-05-31 Dynamische peripheriefunktionsumabbildung auf externe eingangs-ausgangs-verbindungen einer integrierten schaltungsanordnung Active DE602007014043D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US80383506P 2006-06-02 2006-06-02
US11/686,724 US7634596B2 (en) 2006-06-02 2007-03-15 Dynamic peripheral function remapping to external input-output connections of an integrated circuit device
PCT/US2007/070066 WO2007143494A2 (en) 2006-06-02 2007-05-31 Dynamic peripheral function remapping to external input-output connections of an integrated circuit device

Publications (1)

Publication Number Publication Date
DE602007014043D1 true DE602007014043D1 (de) 2011-06-01

Family

ID=38776183

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007014043T Active DE602007014043D1 (de) 2006-06-02 2007-05-31 Dynamische peripheriefunktionsumabbildung auf externe eingangs-ausgangs-verbindungen einer integrierten schaltungsanordnung

Country Status (8)

Country Link
US (1) US7634596B2 (de)
EP (1) EP2030323B1 (de)
KR (1) KR101140304B1 (de)
CN (1) CN101490959B (de)
AT (1) ATE506749T1 (de)
DE (1) DE602007014043D1 (de)
TW (1) TWI408900B (de)
WO (1) WO2007143494A2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080209169A1 (en) * 2005-06-30 2008-08-28 Freescale Semiconductor, Inc Output Stage Circuit Apparatus for a Processor Device and Method Therefor
US8284768B2 (en) * 2005-10-06 2012-10-09 Sierra Wireless, Inc. Dynamic bus-based virtual channel multiplexing device driver architecture
US9921982B2 (en) * 2014-06-05 2018-03-20 Microchip Technology Incorporated Device and method to assign device pin ownership for multi-processor core devices
CN105117360B (zh) * 2015-07-29 2019-01-04 国核自仪系统工程有限公司 基于fpga的接口信号重映射方法
CN105573950B (zh) * 2015-12-25 2018-06-01 山东海量信息技术研究院 一种基于门电路芯片设定vr芯片地址的方法
GB2549927B (en) * 2016-04-25 2018-06-13 Imagination Tech Ltd Circuit architecture
TWI670911B (zh) * 2018-05-01 2019-09-01 瑞昱半導體股份有限公司 靜電放電防護裝置
CN111984575B (zh) * 2019-05-24 2021-12-17 瑞昱半导体股份有限公司 信号传输电路与方法
US11379398B2 (en) 2019-06-04 2022-07-05 Microchip Technology Incorporated Virtual ports for connecting core independent peripherals

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671433A (en) * 1992-09-18 1997-09-23 Vadem Corporation Mappable functions from single chip/multi-chip processors for computers
US5748982A (en) * 1993-04-05 1998-05-05 Packard Bell Nec Apparatus for selecting a user programmable address for an I/O device
DE69430320T2 (de) * 1993-12-13 2002-10-10 Lattice Semiconductor Corp., Hillsboro Anwendungsspezifische module in einem programmierbaren logikbaustein
GB9707861D0 (en) * 1997-04-18 1997-06-04 Certicom Corp Arithmetic processor
US6020760A (en) * 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6125464A (en) * 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
US6300792B1 (en) * 1999-02-06 2001-10-09 Altera Corporation Programmable input/output pin signal multiplexing/demultiplexing circuitry for integrated circuits
JP4593915B2 (ja) * 2002-12-31 2010-12-08 三星電子株式会社 同時両方向入出力回路及び方法

Also Published As

Publication number Publication date
CN101490959B (zh) 2011-07-06
WO2007143494A2 (en) 2007-12-13
TW200820614A (en) 2008-05-01
US7634596B2 (en) 2009-12-15
KR20090018646A (ko) 2009-02-20
KR101140304B1 (ko) 2012-05-02
EP2030323A2 (de) 2009-03-04
TWI408900B (zh) 2013-09-11
WO2007143494A3 (en) 2008-03-13
ATE506749T1 (de) 2011-05-15
CN101490959A (zh) 2009-07-22
EP2030323B1 (de) 2011-04-20
US20070283052A1 (en) 2007-12-06

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