DE602007013477D1 - Elektronischer Schaltkreis, der einen mittels Unterbrechung einer Testkette gesicherten Testmodus umfasst - Google Patents

Elektronischer Schaltkreis, der einen mittels Unterbrechung einer Testkette gesicherten Testmodus umfasst

Info

Publication number
DE602007013477D1
DE602007013477D1 DE602007013477T DE602007013477T DE602007013477D1 DE 602007013477 D1 DE602007013477 D1 DE 602007013477D1 DE 602007013477 T DE602007013477 T DE 602007013477T DE 602007013477 T DE602007013477 T DE 602007013477T DE 602007013477 D1 DE602007013477 D1 DE 602007013477D1
Authority
DE
Germany
Prior art keywords
test
interrupting
electronic circuit
string
test mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007013477T
Other languages
English (en)
Inventor
Frederic Bancel
David Hely
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of DE602007013477D1 publication Critical patent/DE602007013477D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602007013477T 2006-02-10 2007-01-31 Elektronischer Schaltkreis, der einen mittels Unterbrechung einer Testkette gesicherten Testmodus umfasst Active DE602007013477D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0601180A FR2897440A1 (fr) 2006-02-10 2006-02-10 Circuit electronique comprenant un mode de test securise par rupture d'une chaine de test, et procede associe.

Publications (1)

Publication Number Publication Date
DE602007013477D1 true DE602007013477D1 (de) 2011-05-12

Family

ID=37071652

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007013477T Active DE602007013477D1 (de) 2006-02-10 2007-01-31 Elektronischer Schaltkreis, der einen mittels Unterbrechung einer Testkette gesicherten Testmodus umfasst

Country Status (4)

Country Link
US (1) US7676717B2 (de)
EP (1) EP1818677B1 (de)
DE (1) DE602007013477D1 (de)
FR (1) FR2897440A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2461131B (en) * 2008-06-25 2011-04-13 I P Access Ltd Method and apparatus for provisioning of information in a cellular communication network

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9417591D0 (en) * 1994-09-01 1994-10-19 Inmos Ltd Scan testable double edge triggered scan cell
DE69933349T2 (de) * 1998-04-23 2007-05-03 Koninklijke Philips Electronics N.V. Prüfbares ic mit analogen und digitalen schaltungen
US6499124B1 (en) * 1999-05-06 2002-12-24 Xilinx, Inc. Intest security circuit for boundary-scan architecture
US7185249B2 (en) * 2002-04-30 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for secure scan testing
JP2007518988A (ja) * 2004-01-19 2007-07-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 複数のクロックドメインを備える回路のテスティング
FR2865827A1 (fr) * 2004-01-29 2005-08-05 St Microelectronics Sa Securisation du mode de test d'un circuit integre
JP2009505059A (ja) * 2005-08-10 2009-02-05 エヌエックスピー ビー ヴィ 秘密情報を含む集積回路の試験

Also Published As

Publication number Publication date
US20070234156A1 (en) 2007-10-04
FR2897440A1 (fr) 2007-08-17
US7676717B2 (en) 2010-03-09
EP1818677B1 (de) 2011-03-30
EP1818677A1 (de) 2007-08-15

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