DE602006005046D1 - Integrierte Schaltung - Google Patents

Integrierte Schaltung

Info

Publication number
DE602006005046D1
DE602006005046D1 DE602006005046T DE602006005046T DE602006005046D1 DE 602006005046 D1 DE602006005046 D1 DE 602006005046D1 DE 602006005046 T DE602006005046 T DE 602006005046T DE 602006005046 T DE602006005046 T DE 602006005046T DE 602006005046 D1 DE602006005046 D1 DE 602006005046D1
Authority
DE
Germany
Prior art keywords
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006005046T
Other languages
English (en)
Inventor
Takashi Otake
Akihiko Konmoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602006005046D1 publication Critical patent/DE602006005046D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318525—Test of flip-flops or latches
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
DE602006005046T 2006-06-19 2006-10-05 Integrierte Schaltung Active DE602006005046D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006168830A JP2007333681A (ja) 2006-06-19 2006-06-19 集積回路

Publications (1)

Publication Number Publication Date
DE602006005046D1 true DE602006005046D1 (de) 2009-03-19

Family

ID=38474334

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006005046T Active DE602006005046D1 (de) 2006-06-19 2006-10-05 Integrierte Schaltung

Country Status (4)

Country Link
US (1) US20080042714A1 (de)
EP (1) EP1870723B1 (de)
JP (1) JP2007333681A (de)
DE (1) DE602006005046D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080238473A1 (en) * 2007-03-27 2008-10-02 Stmicroelectronics, Inc. Push-Pull Pulse Register Circuit
KR102549438B1 (ko) 2016-09-27 2023-06-29 삼성전자주식회사 순차 회로, 이를 포함하는 스캔 체인 회로 및 집적 회로

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219719A (ja) * 1990-01-24 1991-09-27 Mitsubishi Electric Corp 遅延回路及びそれを用いた半導体装置
DE69840425D1 (de) * 1997-03-27 2009-02-12 Texas Instruments Inc Kontaktlose Prüfung von Anschlusspuffern auf einem Wafer
US6311148B1 (en) 1998-09-09 2001-10-30 Sun Microsystems, Inc. Method for determining static flip-flop setup and hold times
JP3733389B2 (ja) * 1999-02-08 2006-01-11 富士通株式会社 半導体集積回路装置及びそのテスト方法
JP2003043117A (ja) * 2001-08-02 2003-02-13 Fujitsu Ltd 半導体集積回路
US6731158B1 (en) * 2002-06-13 2004-05-04 University Of New Mexico Self regulating body bias generator
GB2415553B (en) * 2003-04-02 2006-07-12 Sun Microsystems Inc Sense amplifying latch with low swing feedback

Also Published As

Publication number Publication date
EP1870723A1 (de) 2007-12-26
JP2007333681A (ja) 2007-12-27
US20080042714A1 (en) 2008-02-21
EP1870723B1 (de) 2009-01-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE