DE602006020500D1 - Justierung einer digitalverzögerungsfunktion einer datenspeichereinheit - Google Patents
Justierung einer digitalverzögerungsfunktion einer datenspeichereinheitInfo
- Publication number
- DE602006020500D1 DE602006020500D1 DE602006020500T DE602006020500T DE602006020500D1 DE 602006020500 D1 DE602006020500 D1 DE 602006020500D1 DE 602006020500 T DE602006020500 T DE 602006020500T DE 602006020500 T DE602006020500 T DE 602006020500T DE 602006020500 D1 DE602006020500 D1 DE 602006020500D1
- Authority
- DE
- Germany
- Prior art keywords
- write
- memory
- clock
- cycle
- adjustment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000013500 data storage Methods 0.000 title 1
- 230000006870 function Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2006/060849 WO2007107182A1 (en) | 2006-03-17 | 2006-03-17 | Adjusting a digital delay function of a data memory unit |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602006020500D1 true DE602006020500D1 (de) | 2011-04-14 |
Family
ID=36685849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006020500T Active DE602006020500D1 (de) | 2006-03-17 | 2006-03-17 | Justierung einer digitalverzögerungsfunktion einer datenspeichereinheit |
Country Status (6)
Country | Link |
---|---|
US (1) | US7933156B2 (de) |
EP (1) | EP1997112B1 (de) |
CN (1) | CN101443852B (de) |
AT (1) | ATE500593T1 (de) |
DE (1) | DE602006020500D1 (de) |
WO (1) | WO2007107182A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8238349B2 (en) | 2008-06-18 | 2012-08-07 | Altera Canada Co. | Method of accessing stored information in multi-framed data transmissions |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5563891A (en) * | 1995-09-05 | 1996-10-08 | Industrial Technology Research Institute | Waiting time jitter reduction by synchronizer stuffing threshold modulation |
US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
US7072433B2 (en) | 2001-07-11 | 2006-07-04 | Micron Technology, Inc. | Delay locked loop fine tune |
JP4417807B2 (ja) * | 2004-08-25 | 2010-02-17 | 株式会社東芝 | エラスティックバッファ |
-
2006
- 2006-03-17 DE DE602006020500T patent/DE602006020500D1/de active Active
- 2006-03-17 WO PCT/EP2006/060849 patent/WO2007107182A1/en active Application Filing
- 2006-03-17 US US12/293,118 patent/US7933156B2/en active Active
- 2006-03-17 AT AT06725144T patent/ATE500593T1/de not_active IP Right Cessation
- 2006-03-17 EP EP06725144A patent/EP1997112B1/de not_active Not-in-force
- 2006-03-17 CN CN2006800546156A patent/CN101443852B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101443852B (zh) | 2012-10-10 |
WO2007107182A1 (en) | 2007-09-27 |
US20090219771A1 (en) | 2009-09-03 |
EP1997112B1 (de) | 2011-03-02 |
US7933156B2 (en) | 2011-04-26 |
EP1997112A1 (de) | 2008-12-03 |
CN101443852A (zh) | 2009-05-27 |
ATE500593T1 (de) | 2011-03-15 |
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