DE602005025534D1 - - Google Patents

Info

Publication number
DE602005025534D1
DE602005025534D1 DE602005025534T DE602005025534T DE602005025534D1 DE 602005025534 D1 DE602005025534 D1 DE 602005025534D1 DE 602005025534 T DE602005025534 T DE 602005025534T DE 602005025534 T DE602005025534 T DE 602005025534T DE 602005025534 D1 DE602005025534 D1 DE 602005025534D1
Authority
DE
Germany
Prior art keywords
silicon
substrate
mono
forming
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005025534T
Other languages
English (en)
Inventor
Philippe Renaud
Isabelle Bertrand
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE602005025534D1 publication Critical patent/DE602005025534D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00611—Processes for the planarisation of structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0118—Processes for the planarization of structures
    • B81C2201/0119—Processes for the planarization of structures involving only addition of materials, i.e. additive planarization

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Recrystallisation Techniques (AREA)
  • Measuring Fluid Pressure (AREA)
  • Element Separation (AREA)
DE602005025534T 2005-01-31 2005-01-31 Active DE602005025534D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2005/000446 WO2006079870A1 (en) 2005-01-31 2005-01-31 Method of fabricating a silicon-on-insulator structure

Publications (1)

Publication Number Publication Date
DE602005025534D1 true DE602005025534D1 (de) 2011-02-03

Family

ID=34960619

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005025534T Active DE602005025534D1 (de) 2005-01-31 2005-01-31

Country Status (6)

Country Link
US (1) US20080213981A1 (de)
EP (1) EP1846321B1 (de)
AT (1) ATE492510T1 (de)
DE (1) DE602005025534D1 (de)
TW (1) TW200701339A (de)
WO (1) WO2006079870A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2999801B1 (fr) 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
DE102015200176A1 (de) * 2015-01-09 2016-07-14 Robert Bosch Gmbh Verfahren zum Erzeugen des Schichtaufbaus eines Halbleiterbauelements
CN110085550A (zh) * 2018-01-26 2019-08-02 沈阳硅基科技有限公司 一种半导体产品用绝缘层结构及其制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4323417A (en) * 1980-05-06 1982-04-06 Texas Instruments Incorporated Method of producing monocrystal on insulator
JPS5831515A (ja) 1981-08-18 1983-02-24 Nec Corp 半導体薄膜の製造方法
JPS58130517A (ja) * 1982-01-29 1983-08-04 Hitachi Ltd 単結晶薄膜の製造方法
US4559102A (en) * 1983-05-09 1985-12-17 Sony Corporation Method for recrystallizing a polycrystalline, amorphous or small grain material
JPS61198712A (ja) * 1985-02-28 1986-09-03 Fujitsu Ltd 半導体装置の製造方法
US5095401A (en) * 1989-01-13 1992-03-10 Kopin Corporation SOI diaphragm sensor
US5177661A (en) 1989-01-13 1993-01-05 Kopin Corporation SOI diaphgram sensor
JPH0478123A (ja) * 1990-07-20 1992-03-12 Fujitsu Ltd 半導体装置の製造方法
US5186785A (en) * 1991-04-05 1993-02-16 The United States Of America As Represented By The Secretary Of The Air Force Zone melted recrystallized silicon on diamond
US5747353A (en) * 1996-04-16 1998-05-05 National Semiconductor Corporation Method of making surface micro-machined accelerometer using silicon-on-insulator technology
EP0822415B1 (de) 1996-07-31 2003-03-26 STMicroelectronics S.r.l. Integrierter kapazitiver Halbleiter-Beschleunigungsmessaufnehmer sowie Verfahren zu seiner Herstellung
FR2764706B1 (fr) * 1997-06-17 1999-07-09 Commissariat Energie Atomique Accelerometre miniaturise du type a compensation par ressort de l'effet de la pesanteur et son procede de fabrication
US6130464A (en) * 1997-09-08 2000-10-10 Roxburgh Ltd. Latching microaccelerometer
US6105427A (en) 1998-07-31 2000-08-22 Litton Systems, Inc. Micro-mechanical semiconductor accelerometer
FI119078B (fi) 2002-02-12 2008-07-15 Nokia Corp Kiihtyvyysanturi

Also Published As

Publication number Publication date
US20080213981A1 (en) 2008-09-04
EP1846321B1 (de) 2010-12-22
EP1846321A1 (de) 2007-10-24
TW200701339A (en) 2007-01-01
ATE492510T1 (de) 2011-01-15
WO2006079870A1 (en) 2006-08-03

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DE602005025534D1 (de)