DE602004023127D1 - Elektronsiche schaltung mit einer fifo-pipeline - Google Patents
Elektronsiche schaltung mit einer fifo-pipelineInfo
- Publication number
- DE602004023127D1 DE602004023127D1 DE602004023127T DE602004023127T DE602004023127D1 DE 602004023127 D1 DE602004023127 D1 DE 602004023127D1 DE 602004023127 T DE602004023127 T DE 602004023127T DE 602004023127 T DE602004023127 T DE 602004023127T DE 602004023127 D1 DE602004023127 D1 DE 602004023127D1
- Authority
- DE
- Germany
- Prior art keywords
- line
- stage
- handshake
- output
- chains
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04100087 | 2004-01-13 | ||
PCT/IB2004/052932 WO2005069121A1 (en) | 2004-01-13 | 2004-12-29 | Electronic circuit with a fifo pipeline |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602004023127D1 true DE602004023127D1 (de) | 2009-10-22 |
Family
ID=34778215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004023127T Expired - Fee Related DE602004023127D1 (de) | 2004-01-13 | 2004-12-29 | Elektronsiche schaltung mit einer fifo-pipeline |
Country Status (7)
Country | Link |
---|---|
US (1) | US20070113049A1 (de) |
EP (1) | EP1714209B1 (de) |
JP (1) | JP2007518178A (de) |
CN (1) | CN1902580A (de) |
AT (1) | ATE442623T1 (de) |
DE (1) | DE602004023127D1 (de) |
WO (1) | WO2005069121A1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007535064A (ja) * | 2004-04-28 | 2007-11-29 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 非同期/同期インタフェースを備える回路 |
CN101258463A (zh) * | 2005-09-05 | 2008-09-03 | Nxp股份有限公司 | 异步脉动流水线 |
US9141567B2 (en) | 2006-07-11 | 2015-09-22 | Harman International Industries, Incorporated | Serial communication input output interface engine |
US8074053B2 (en) | 2006-07-11 | 2011-12-06 | Harman International Industries, Incorporated | Dynamic instruction and data updating architecture |
US8429384B2 (en) | 2006-07-11 | 2013-04-23 | Harman International Industries, Incorporated | Interleaved hardware multithreading processor architecture |
WO2008008661A2 (en) * | 2006-07-11 | 2008-01-17 | Harman International Industries, Incorporated | Interleaved hardware multithreading processor architecture and dynamic instruction and data updating architecture |
WO2013020114A1 (en) | 2011-08-03 | 2013-02-07 | Cornell University | Energy-efficient pipeline circuit templates for high performance asynchronous circuits |
CN102929830A (zh) * | 2012-11-08 | 2013-02-13 | 浙江绍兴苏泊尔生活电器有限公司 | 一种软件模拟快速通信协议 |
CN109976704A (zh) * | 2019-03-29 | 2019-07-05 | 西安电子科技大学 | 一种基于fpga的级联fifo模块的设计方法 |
CN113489482B (zh) * | 2021-07-06 | 2023-10-20 | 北京中科芯蕊科技有限公司 | 基于Mousetrap的异步微流水线数据流控制器 |
CN115800992B (zh) * | 2023-02-07 | 2023-06-02 | 浪潮电子信息产业股份有限公司 | 一种握手信号的拆分电路、方法、装置、设备及存储介质 |
CN116384309B (zh) * | 2023-05-31 | 2023-08-11 | 华中科技大学 | 一种应用于低功耗芯片设计的四相锁存异步握手电路 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU8495098A (en) * | 1997-07-16 | 1999-02-10 | California Institute Of Technology | Improved devices and methods for asynchronous processing |
US6226698B1 (en) * | 1997-11-10 | 2001-05-01 | Sun Microsystems, Inc. | Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO |
US6128678A (en) * | 1998-08-28 | 2000-10-03 | Theseus Logic, Inc. | FIFO using asynchronous logic to interface between clocked logic circuits |
WO2001082064A2 (en) * | 2000-04-25 | 2001-11-01 | The Trustees Of Columbia University In The City Of New York | Circuits and methods for high-capacity asynchronous pipeline processing |
US6850092B2 (en) * | 2000-06-09 | 2005-02-01 | The Trustees Of Columbia University | Low latency FIFO circuits for mixed asynchronous and synchronous systems |
US6590424B2 (en) * | 2000-07-12 | 2003-07-08 | The Trustees Of Columbia University In The City Of New York | High-throughput asynchronous dynamic pipelines |
US6356117B1 (en) * | 2000-09-29 | 2002-03-12 | Sun Microsystems, Inc. | Asynchronously controlling data transfers within a circuit |
WO2002035346A1 (en) * | 2000-10-23 | 2002-05-02 | The Trustees Of Columbia University In The City Of New York | Asynchronous pipeline with latch controllers |
US20020078328A1 (en) * | 2000-12-14 | 2002-06-20 | International Business Machines Corporation | Pulse-controlled micropipeline architecture |
US6557161B2 (en) * | 2001-06-28 | 2003-04-29 | Sun Microsystems, Inc. | Method for prototyping asynchronous circuits using synchronous devices |
US7487300B2 (en) * | 2003-06-16 | 2009-02-03 | Nxp B.V. | Data processing circuit with multiplexed memory |
-
2004
- 2004-12-29 CN CNA2004800402983A patent/CN1902580A/zh active Pending
- 2004-12-29 AT AT04806634T patent/ATE442623T1/de not_active IP Right Cessation
- 2004-12-29 DE DE602004023127T patent/DE602004023127D1/de not_active Expired - Fee Related
- 2004-12-29 US US10/585,802 patent/US20070113049A1/en not_active Abandoned
- 2004-12-29 JP JP2006548452A patent/JP2007518178A/ja not_active Withdrawn
- 2004-12-29 WO PCT/IB2004/052932 patent/WO2005069121A1/en not_active Application Discontinuation
- 2004-12-29 EP EP04806634A patent/EP1714209B1/de not_active Not-in-force
Also Published As
Publication number | Publication date |
---|---|
EP1714209B1 (de) | 2009-09-09 |
ATE442623T1 (de) | 2009-09-15 |
CN1902580A (zh) | 2007-01-24 |
EP1714209A1 (de) | 2006-10-25 |
US20070113049A1 (en) | 2007-05-17 |
WO2005069121A1 (en) | 2005-07-28 |
JP2007518178A (ja) | 2007-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE602004023127D1 (de) | Elektronsiche schaltung mit einer fifo-pipeline | |
KR100783687B1 (ko) | 래치 제어기를 갖는 비동기 파이프라인 | |
WO2022012252A1 (zh) | 时钟树、哈希引擎、计算芯片、算力板和数据处理设备 | |
US8872544B2 (en) | Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits | |
US9100315B2 (en) | Source asynchronous signaling | |
TWI784457B (zh) | 時鐘電路系統、計算晶片、算力板和資料處理設備 | |
CN111930682A (zh) | 时钟树、哈希引擎、计算芯片、算力板和数字货币挖矿机 | |
CN212160484U (zh) | 时钟电路系统、计算芯片、算力板和数字货币挖矿机 | |
CN212515801U (zh) | 时钟树、哈希引擎、计算芯片、算力板和加密货币挖矿机 | |
CN111651403A (zh) | 时钟树、哈希引擎、计算芯片、算力板和数字货币挖矿机 | |
CN212515800U (zh) | 时钟树、哈希引擎、计算芯片、算力板和加密货币挖矿机 | |
CN212515799U (zh) | 时钟树、哈希引擎、计算芯片、算力板和加密货币挖矿机 | |
WO2005091130A3 (en) | Instruction pipeline | |
Maity et al. | Design of quantum cost efficient 4-bit reversible universal shift register | |
TW200746170A (en) | Memory circuit | |
WO2014026451A1 (zh) | 一种有限域求逆器 | |
HV et al. | Reduced Complexity Hybrid Ripple Carry Lookahead Adder | |
WO2022105252A1 (zh) | 运算核、计算芯片和数据处理设备 | |
Sravani et al. | A high performance early acknowledged asynchronous pipeline using hybrid-logic encoding | |
Yi et al. | The new architecture of radix-4 Chinese abacus adder | |
Nandhini et al. | Implementation of Normal Urdhva Tiryakbhayam Multiplier in VLSI | |
Dong et al. | Hardware implementation of double basis multiplier using TMVP approach over GF (2 m) | |
Du et al. | Research and Design of Pipeline Register Structure Based on Coarse-grained Reconfigurable Array | |
Arun-Kumar | Generalising Bisimulations | |
Girčys et al. | Two complete finitary sequent calculi for reflexive common knowledge |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |