DE602004021931D1 - Fehlertolerante datenspeicherschaltung - Google Patents

Fehlertolerante datenspeicherschaltung

Info

Publication number
DE602004021931D1
DE602004021931D1 DE602004021931T DE602004021931T DE602004021931D1 DE 602004021931 D1 DE602004021931 D1 DE 602004021931D1 DE 602004021931 T DE602004021931 T DE 602004021931T DE 602004021931 T DE602004021931 T DE 602004021931T DE 602004021931 D1 DE602004021931 D1 DE 602004021931D1
Authority
DE
Germany
Prior art keywords
data memory
memory circuit
fault tolerant
tolerant data
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602004021931T
Other languages
English (en)
Inventor
Philip S Ng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of DE602004021931D1 publication Critical patent/DE602004021931D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
DE602004021931T 2003-06-02 2004-05-11 Fehlertolerante datenspeicherschaltung Expired - Fee Related DE602004021931D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/453,160 US7181650B2 (en) 2003-06-02 2003-06-02 Fault tolerant data storage circuit
PCT/US2004/014693 WO2004109751A2 (en) 2003-06-02 2004-05-11 Fault tolerant data storage circuit

Publications (1)

Publication Number Publication Date
DE602004021931D1 true DE602004021931D1 (de) 2009-08-20

Family

ID=33510378

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004021931T Expired - Fee Related DE602004021931D1 (de) 2003-06-02 2004-05-11 Fehlertolerante datenspeicherschaltung

Country Status (6)

Country Link
US (1) US7181650B2 (de)
EP (1) EP1634172B1 (de)
CN (2) CN102135924A (de)
DE (1) DE602004021931D1 (de)
TW (1) TWI330939B (de)
WO (1) WO2004109751A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8913450B2 (en) * 2012-11-19 2014-12-16 Qualcomm Incorporated Memory cell array with reserved sector for storing configuration information
CN106873569B (zh) * 2015-12-14 2019-05-21 中国航空工业第六一八研究所 一种基于rs触发器的bit故障锁存方法
CN113921068B (zh) * 2021-09-28 2023-07-14 合肥大唐存储科技有限公司 一种寄存器保护电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3032333A1 (de) * 1980-08-27 1982-04-22 Siemens AG, 1000 Berlin und 8000 München Monolithische statische speicherzelle und verfahren zu ihrem betrieb
JPS5798197A (en) 1980-12-11 1982-06-18 Fujitsu Ltd Multiplexing memory device
US5572620A (en) * 1993-07-29 1996-11-05 Honeywell Inc. Fault-tolerant voter system for output data from a plurality of non-synchronized redundant processors
US5799022A (en) * 1996-07-01 1998-08-25 Sun Microsystems, Inc. Faulty module location in a fault tolerant computer system
GB9705436D0 (en) * 1997-03-15 1997-04-30 Sharp Kk Fault tolerant circuit arrangements
US6289477B1 (en) * 1998-04-28 2001-09-11 Adaptec, Inc. Fast-scan-flop and integrated circuit device incorporating the same
US6104211A (en) * 1998-09-11 2000-08-15 Xilinx, Inc. System for preventing radiation failures in programmable logic devices
US6359477B1 (en) * 1999-06-03 2002-03-19 Texas Instruments Incorporated Low power driver design
US6484271B1 (en) * 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6144604A (en) * 1999-11-12 2000-11-07 Haller; Haggai Haim Simultaneous addressing using single-port RAMs
US6446229B1 (en) * 2000-06-29 2002-09-03 Intel Corporation Method and apparatus for integrated flip-flop to support two test modes
JP3807593B2 (ja) * 2000-07-24 2006-08-09 株式会社ルネサステクノロジ クロック生成回路および制御方法並びに半導体記憶装置

Also Published As

Publication number Publication date
TWI330939B (en) 2010-09-21
CN102135924A (zh) 2011-07-27
TW200503416A (en) 2005-01-16
WO2004109751A3 (en) 2005-12-29
EP1634172A4 (de) 2006-08-30
EP1634172A2 (de) 2006-03-15
US20040255196A1 (en) 2004-12-16
EP1634172B1 (de) 2009-07-08
US7181650B2 (en) 2007-02-20
CN1836215A (zh) 2006-09-20
WO2004109751A2 (en) 2004-12-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee