DE602004018913D1 - Cachespeicher-Steuereinheit und -Steuerverfahren - Google Patents

Cachespeicher-Steuereinheit und -Steuerverfahren

Info

Publication number
DE602004018913D1
DE602004018913D1 DE602004018913T DE602004018913T DE602004018913D1 DE 602004018913 D1 DE602004018913 D1 DE 602004018913D1 DE 602004018913 T DE602004018913 T DE 602004018913T DE 602004018913 T DE602004018913 T DE 602004018913T DE 602004018913 D1 DE602004018913 D1 DE 602004018913D1
Authority
DE
Germany
Prior art keywords
controller
cache
cache controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004018913T
Other languages
English (en)
Inventor
Shuichi Yoshizawa
Hiroyuki Kojima
Masaki Ukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602004018913D1 publication Critical patent/DE602004018913D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE602004018913T 2004-07-29 2004-11-19 Cachespeicher-Steuereinheit und -Steuerverfahren Active DE602004018913D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004221156A JP4575065B2 (ja) 2004-07-29 2004-07-29 キャッシュメモリ制御装置、キャッシュメモリ制御方法、中央処理装置、情報処理装置、中央制御方法

Publications (1)

Publication Number Publication Date
DE602004018913D1 true DE602004018913D1 (de) 2009-02-26

Family

ID=35170065

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004018913T Active DE602004018913D1 (de) 2004-07-29 2004-11-19 Cachespeicher-Steuereinheit und -Steuerverfahren

Country Status (4)

Country Link
US (1) US7552287B2 (de)
EP (2) EP1942416B1 (de)
JP (1) JP4575065B2 (de)
DE (1) DE602004018913D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2159704B1 (de) 2007-06-20 2013-06-26 Fujitsu Limited Cache-speichersteuereinrichtung und pipeline-steuerverfahren
US8171225B2 (en) * 2007-06-28 2012-05-01 Intel Corporation Cache for a multi thread and multi core system and methods thereof
US20100332690A1 (en) * 2008-01-29 2010-12-30 Panasonic Corporation Processor performance analysis device, method, and simulator
WO2009104240A1 (ja) * 2008-02-18 2009-08-27 富士通株式会社 演算処理装置および演算処理装置の制御方法
JP2010191754A (ja) * 2009-02-19 2010-09-02 Mitsubishi Electric Corp キャッシュ記憶装置
JP5444889B2 (ja) * 2009-06-30 2014-03-19 富士通株式会社 演算処理装置および演算処理装置の制御方法
JP5609092B2 (ja) * 2009-12-09 2014-10-22 富士通株式会社 演算処理装置及び演算処理装置の制御方法
KR101402560B1 (ko) 2009-12-25 2014-05-30 후지쯔 가부시끼가이샤 연산 처리 장치
JP5730126B2 (ja) 2011-05-18 2015-06-03 キヤノン株式会社 データ供給装置、キャッシュ装置、データ供給方法、キャッシュ方法およびプログラム
JP6711167B2 (ja) 2016-06-22 2020-06-17 富士通株式会社 演算処理装置および演算処理装置の制御方法
CN114661442A (zh) * 2021-05-08 2022-06-24 支付宝(杭州)信息技术有限公司 处理方法及装置、处理器、电子设备及存储介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63751A (ja) * 1986-06-20 1988-01-05 Fujitsu Ltd プリフエツチ制御方式
JPH02133842A (ja) 1988-11-15 1990-05-23 Fujitsu Ltd 中間バッファプリフェッチ制御方式
JPH04270432A (ja) * 1991-01-25 1992-09-25 Fujitsu Ltd ディスクキャッシュ制御方式
JP3566319B2 (ja) * 1993-06-20 2004-09-15 株式会社リコー 情報記憶装置
JP3284508B2 (ja) * 1994-02-08 2002-05-20 富士通株式会社 データ先読み制御装置
US6643745B1 (en) * 1998-03-31 2003-11-04 Intel Corporation Method and apparatus for prefetching data into cache
WO2000031642A1 (de) * 1998-11-25 2000-06-02 Fujitsu Siemens Computers Gmbh Cache-speichereinrichtung

Also Published As

Publication number Publication date
JP4575065B2 (ja) 2010-11-04
US20060026366A1 (en) 2006-02-02
EP1622026A2 (de) 2006-02-01
EP1942416A2 (de) 2008-07-09
EP1622026B1 (de) 2009-01-07
EP1942416B1 (de) 2011-06-29
EP1622026A3 (de) 2006-09-13
EP1942416A3 (de) 2008-09-03
JP2006040090A (ja) 2006-02-09
US7552287B2 (en) 2009-06-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE