DE602004008080D1 - Mit einer Quelle synchrone Abtastung - Google Patents

Mit einer Quelle synchrone Abtastung

Info

Publication number
DE602004008080D1
DE602004008080D1 DE602004008080T DE602004008080T DE602004008080D1 DE 602004008080 D1 DE602004008080 D1 DE 602004008080D1 DE 602004008080 T DE602004008080 T DE 602004008080T DE 602004008080 T DE602004008080 T DE 602004008080T DE 602004008080 D1 DE602004008080 D1 DE 602004008080D1
Authority
DE
Germany
Prior art keywords
source synchronous
synchronous sampling
sampling
source
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004008080T
Other languages
English (en)
Other versions
DE602004008080T2 (de
Inventor
Markus Rottacker
Bernd Laquai
Klaus Behrens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE602004008080D1 publication Critical patent/DE602004008080D1/de
Application granted granted Critical
Publication of DE602004008080T2 publication Critical patent/DE602004008080T2/de
Anticipated expiration legal-status Critical
Active legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0008Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922Timing generation or clock distribution
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/3193Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937Timing aspects, e.g. measuring propagation delay
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033Correction by delay

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE602004008080T 2004-10-27 2004-10-27 Mit einer Quelle synchrone Abtastung Active DE602004008080T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04105327A EP1653650B1 (de) 2004-10-27 2004-10-27 Mit einer Quelle synchrone Abtastung

Publications (2)

Publication Number Publication Date
DE602004008080D1 true DE602004008080D1 (de) 2007-09-20
DE602004008080T2 DE602004008080T2 (de) 2008-04-17

Family

ID=34929768

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004008080T Active DE602004008080T2 (de) 2004-10-27 2004-10-27 Mit einer Quelle synchrone Abtastung

Country Status (4)

Country Link
US (1) US7355378B2 (de)
EP (1) EP1653650B1 (de)
JP (1) JP4690854B2 (de)
DE (1) DE602004008080T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8327204B2 (en) * 2005-10-27 2012-12-04 Dft Microsystems, Inc. High-speed transceiver tester incorporating jitter injection
US7813297B2 (en) * 2006-07-14 2010-10-12 Dft Microsystems, Inc. High-speed signal testing system having oscilloscope functionality
US7681091B2 (en) * 2006-07-14 2010-03-16 Dft Microsystems, Inc. Signal integrity measurement systems and methods using a predominantly digital time-base generator
JP2010518760A (ja) * 2007-02-09 2010-05-27 ディー・エフ・ティー・マイクロシステムズ・インコーポレーテッド ハイスピード・シリアル・リンクのミッション環境における、該ハイスピード・シリアル・リンクの物理層テスティングのためのシステム及び方法
US7917319B2 (en) * 2008-02-06 2011-03-29 Dft Microsystems Inc. Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits
CN102099700A (zh) * 2008-08-01 2011-06-15 株式会社爱德万测试 测试装置
TWI442241B (zh) * 2011-01-12 2014-06-21 Zeroplus Technology Co Ltd Data Synchronization System and Method for Multi - measure Instrument
FR2979506B1 (fr) * 2011-08-30 2013-08-30 Bull Sas Procede de synchronisation d'une grappe de serveurs et grappe de serveurs mettant en oeuvre ce procede
US9094840B2 (en) * 2013-01-10 2015-07-28 Apple Inc. Methods for testing receiver sensitivity of wireless electronic devices
CN103309397B (zh) * 2013-06-17 2015-11-18 杭州锐达数字技术有限公司 基于usb的数据采集设备的同步采样方法
JP2015037307A (ja) * 2013-08-16 2015-02-23 富士通株式会社 無線通信装置及び送信タイミング調整プログラム
CN106406174B (zh) * 2016-09-29 2018-07-24 中国电子科技集团公司第二十九研究所 一种多模块多通道采集同步系统及工作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0818414A (ja) * 1994-04-26 1996-01-19 Hitachi Ltd 信号処理用遅延回路
GB2302191B (en) * 1995-02-24 2000-05-10 Advantest Corp Bit error measurement system.
JP4063392B2 (ja) * 1998-03-26 2008-03-19 富士通株式会社 信号伝送システム
JP2001306176A (ja) * 2000-04-26 2001-11-02 Nec Corp クロック位相自動調整回路
WO2003060533A1 (fr) * 2002-01-10 2003-07-24 Advantest Corporation Dispositif pour tester la lsi a mesurer, analyseur de gigue et detecteur de dephasage
GB2397708A (en) * 2002-09-11 2004-07-28 Sun Microsystems Inc Source synchronous interface using variable digital and analog delay lines
US6791360B2 (en) * 2002-09-11 2004-09-14 Sun Microsystems, Inc. Source synchronous interface using variable digital data delay lines

Also Published As

Publication number Publication date
DE602004008080T2 (de) 2008-04-17
JP4690854B2 (ja) 2011-06-01
JP2006129488A (ja) 2006-05-18
EP1653650B1 (de) 2007-08-08
EP1653650A1 (de) 2006-05-03
US20060114978A1 (en) 2006-06-01
US7355378B2 (en) 2008-04-08

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US

8364 No opposition during term of opposition
R082 Change of representative

Ref document number: 1653650

Country of ref document: EP

Representative=s name: SCHOPPE, ZIMMERMANN, STOECKELER, ZINKLER & PARTNER