DE602004006700D1 - Serieller Speicher mit Mitteln zum Schutz eines erweiterten Speicherfeldes während einer Schreiboperation - Google Patents

Serieller Speicher mit Mitteln zum Schutz eines erweiterten Speicherfeldes während einer Schreiboperation

Info

Publication number
DE602004006700D1
DE602004006700D1 DE602004006700T DE602004006700T DE602004006700D1 DE 602004006700 D1 DE602004006700 D1 DE 602004006700D1 DE 602004006700 T DE602004006700 T DE 602004006700T DE 602004006700 T DE602004006700 T DE 602004006700T DE 602004006700 D1 DE602004006700 D1 DE 602004006700D1
Authority
DE
Germany
Prior art keywords
protecting
write operation
array during
memory array
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004006700T
Other languages
English (en)
Inventor
Sebastien Zink
Paola Cavalieri
Bruno Leconte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0314622A external-priority patent/FR2863764A1/fr
Priority claimed from FR0314628A external-priority patent/FR2863765A1/fr
Priority claimed from FR0314621A external-priority patent/FR2863766A1/fr
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of DE602004006700D1 publication Critical patent/DE602004006700D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
DE602004006700T 2003-12-12 2004-12-08 Serieller Speicher mit Mitteln zum Schutz eines erweiterten Speicherfeldes während einer Schreiboperation Active DE602004006700D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0314622A FR2863764A1 (fr) 2003-12-12 2003-12-12 Memoire serie comprenant des moyens de protection d'un plan memoire entendu pendant une operation d'ecriture
FR0314628A FR2863765A1 (fr) 2003-12-12 2003-12-12 Procede de realisation d'un plan memoire etendu au moyen d'une pluralite de memoires serie
FR0314621A FR2863766A1 (fr) 2003-12-12 2003-12-12 Memoire serie comprenant des moyens d'integration dans un plan memoire etendu

Publications (1)

Publication Number Publication Date
DE602004006700D1 true DE602004006700D1 (de) 2007-07-12

Family

ID=34527436

Family Applications (2)

Application Number Title Priority Date Filing Date
DE602004006700T Active DE602004006700D1 (de) 2003-12-12 2004-12-08 Serieller Speicher mit Mitteln zum Schutz eines erweiterten Speicherfeldes während einer Schreiboperation
DE602004005806T Active DE602004005806T2 (de) 2003-12-12 2004-12-08 Serieller Speicher mit Mitteln zur Integration eines erweiterten Speicherfeldes

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE602004005806T Active DE602004005806T2 (de) 2003-12-12 2004-12-08 Serieller Speicher mit Mitteln zur Integration eines erweiterten Speicherfeldes

Country Status (3)

Country Link
US (3) US7290078B2 (de)
EP (3) EP1542234A3 (de)
DE (2) DE602004006700D1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101620128B1 (ko) * 2008-12-30 2016-05-12 마이크론 테크놀로지, 인크. 직렬 비휘발성 메모리를 위한 향상된 어드레싱 능력
US8898439B2 (en) * 2009-07-17 2014-11-25 Macronix International Co., Ltd. Serial flash memory and address transmission method thereof
US8677100B2 (en) * 2009-07-17 2014-03-18 Macronix International Co., Ltd. Serial memory interface for extended address space
KR101903095B1 (ko) * 2011-11-21 2018-10-02 삼성전자주식회사 불휘발성 메모리 장치 및 불휘발성 메모리 장치를 제어하는 컨트롤러의 동작 방법
US11494317B1 (en) 2020-12-29 2022-11-08 Waymo Llc Memory validation

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US4128883A (en) 1977-09-30 1978-12-05 Ncr Corporation Shared busy means in a common bus environment
JPS5847793B2 (ja) * 1979-11-12 1983-10-25 富士通株式会社 半導体記憶装置
US4665506A (en) 1983-01-03 1987-05-12 Texas Instruments Incorporated Memory system with write protection
US4931997A (en) * 1987-03-16 1990-06-05 Hitachi Ltd. Semiconductor memory having storage buffer to save control data during bulk erase
US4908789A (en) 1987-04-01 1990-03-13 International Business Machines Corporation Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range
US4905137A (en) * 1987-12-18 1990-02-27 North American Philips Corporation Signetics Division Data bus control of ROM units in information processing system
US5357621A (en) * 1990-09-04 1994-10-18 Hewlett-Packard Company Serial architecture for memory module control
US5430859A (en) * 1991-07-26 1995-07-04 Sundisk Corporation Solid state memory system including plural memory chips and a serialized bus
JP3310011B2 (ja) * 1992-03-30 2002-07-29 株式会社東芝 半導体メモリおよびこれを使用した半導体メモリボード
US5428566A (en) * 1993-10-27 1995-06-27 Intel Corporation Nonvolatile memory card with ready and busy indication and pin count minimization
JP3059349B2 (ja) * 1994-12-19 2000-07-04 シャープ株式会社 Ｉｃカード、及びフラッシュメモリの並列処理方法
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
KR0145222B1 (ko) * 1995-05-20 1998-08-17 김광호 반도체 메모리장치의 메모리 셀 테스트 제어회로 및 방법
US5592488A (en) * 1995-06-07 1997-01-07 Micron Technology, Inc. Method and apparatus for pipelined multiplexing employing analog delays for a multiport interface
US5895480A (en) * 1995-10-10 1999-04-20 Holtek Microelectronics, Inc. Method of and means for accessing an address by respectively substracting base addresses of memory integrated circuits from an access address
US5857214A (en) * 1995-12-18 1999-01-05 Advanced Micro Devices, Inc. Microprocessor with a fixed cache size selected from a predesigned set of sizes
JP3850067B2 (ja) * 1996-04-24 2006-11-29 株式会社ルネサステクノロジ メモリシステムおよびそれに用いられる半導体記憶装置
US6279069B1 (en) * 1996-12-26 2001-08-21 Intel Corporation Interface for flash EEPROM memory arrays
US5937423A (en) * 1996-12-26 1999-08-10 Intel Corporation Register interface for flash EEPROM memory arrays
US6175891B1 (en) * 1997-04-23 2001-01-16 Micron Technology, Inc. System and method for assigning addresses to memory devices
US6442644B1 (en) * 1997-08-11 2002-08-27 Advanced Memory International, Inc. Memory system having synchronous-link DRAM (SLDRAM) devices and controller
US6247084B1 (en) * 1997-10-08 2001-06-12 Lsi Logic Corporation Integrated circuit with unified memory system and dual bus architecture
US6377502B1 (en) * 1999-05-10 2002-04-23 Kabushiki Kaisha Toshiba Semiconductor device that enables simultaneous read and write/erase operation
JP2001167586A (ja) * 1999-12-08 2001-06-22 Toshiba Corp 不揮発性半導体メモリ装置
TW561491B (en) * 2001-06-29 2003-11-11 Toshiba Corp Semiconductor memory device
KR100437467B1 (ko) * 2002-07-03 2004-06-23 삼성전자주식회사 연속 버스트 읽기 동작 모드를 갖는 멀티 칩 시스템
US20060014125A1 (en) * 2004-07-14 2006-01-19 St Clair John Q Walking through walls training system

Also Published As

Publication number Publication date
US7290078B2 (en) 2007-10-30
EP1542234A3 (de) 2008-08-27
US20060056262A1 (en) 2006-03-16
EP1542233B1 (de) 2007-05-30
DE602004005806T2 (de) 2008-01-10
EP1542233A1 (de) 2005-06-15
DE602004005806D1 (de) 2007-05-24
US20060056261A1 (en) 2006-03-16
US7330381B2 (en) 2008-02-12
US20070300015A1 (en) 2007-12-27
EP1542130B1 (de) 2007-04-11
EP1542130A1 (de) 2005-06-15
US7793033B2 (en) 2010-09-07
EP1542234A2 (de) 2005-06-15

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Legal Events

Date Code Title Description
8332 No legal effect for de