DE602004004533D1 - Phasenmischschaltung mit verzögertem regelkreis - Google Patents
Phasenmischschaltung mit verzögertem regelkreisInfo
- Publication number
- DE602004004533D1 DE602004004533D1 DE602004004533T DE602004004533T DE602004004533D1 DE 602004004533 D1 DE602004004533 D1 DE 602004004533D1 DE 602004004533 T DE602004004533 T DE 602004004533T DE 602004004533 T DE602004004533 T DE 602004004533T DE 602004004533 D1 DE602004004533 D1 DE 602004004533D1
- Authority
- DE
- Germany
- Prior art keywords
- control circuit
- phase mixing
- delayed control
- delayed
- mixing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US696920 | 2003-10-30 | ||
US10/696,920 US20050093594A1 (en) | 2003-10-30 | 2003-10-30 | Delay locked loop phase blender circuit |
PCT/EP2004/010941 WO2005048455A1 (en) | 2003-10-30 | 2004-09-30 | Delayed locked loop phase blender circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004004533D1 true DE602004004533D1 (de) | 2007-03-15 |
DE602004004533T2 DE602004004533T2 (de) | 2007-11-15 |
Family
ID=34550227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004004533T Expired - Fee Related DE602004004533T2 (de) | 2003-10-30 | 2004-09-30 | Phasenmischschaltung mit verzögertem regelkreis |
Country Status (7)
Country | Link |
---|---|
US (1) | US20050093594A1 (de) |
EP (1) | EP1634375B1 (de) |
JP (1) | JP2007502067A (de) |
KR (1) | KR100817962B1 (de) |
CN (1) | CN1846355A (de) |
DE (1) | DE602004004533T2 (de) |
WO (1) | WO2005048455A1 (de) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7394445B2 (en) * | 2002-11-12 | 2008-07-01 | Power-One, Inc. | Digital power manager for controlling and monitoring an array of point-of-load regulators |
US7049798B2 (en) * | 2002-11-13 | 2006-05-23 | Power-One, Inc. | System and method for communicating with a voltage regulator |
US7456617B2 (en) * | 2002-11-13 | 2008-11-25 | Power-One, Inc. | System for controlling and monitoring an array of point-of-load regulators by a host |
US6833691B2 (en) | 2002-11-19 | 2004-12-21 | Power-One Limited | System and method for providing digital pulse width modulation |
US7737961B2 (en) * | 2002-12-21 | 2010-06-15 | Power-One, Inc. | Method and system for controlling and monitoring an array of point-of-load regulators |
US7249267B2 (en) * | 2002-12-21 | 2007-07-24 | Power-One, Inc. | Method and system for communicating filter compensation coefficients for a digital power control system |
US7673157B2 (en) | 2002-12-21 | 2010-03-02 | Power-One, Inc. | Method and system for controlling a mixed array of point-of-load regulators through a bus translator |
US7743266B2 (en) * | 2002-12-21 | 2010-06-22 | Power-One, Inc. | Method and system for optimizing filter compensation coefficients for a digital power control system |
US7836322B2 (en) * | 2002-12-21 | 2010-11-16 | Power-One, Inc. | System for controlling an array of point-of-load regulators and auxiliary devices |
US7882372B2 (en) * | 2002-12-21 | 2011-02-01 | Power-One, Inc. | Method and system for controlling and monitoring an array of point-of-load regulators |
US7266709B2 (en) * | 2002-12-21 | 2007-09-04 | Power-One, Inc. | Method and system for controlling an array of point-of-load regulators and auxiliary devices |
US7373527B2 (en) * | 2002-12-23 | 2008-05-13 | Power-One, Inc. | System and method for interleaving point-of-load regulators |
US7023190B2 (en) * | 2003-02-10 | 2006-04-04 | Power-One, Inc. | ADC transfer function providing improved dynamic regulation in a switched mode power supply |
US7710092B2 (en) * | 2003-02-10 | 2010-05-04 | Power-One, Inc. | Self tracking ADC for digital power supply control systems |
US7080265B2 (en) * | 2003-03-14 | 2006-07-18 | Power-One, Inc. | Voltage set point control scheme |
US6936999B2 (en) * | 2003-03-14 | 2005-08-30 | Power-One Limited | System and method for controlling output-timing parameters of power converters |
US6958592B2 (en) * | 2003-11-26 | 2005-10-25 | Power-One, Inc. | Adaptive delay control circuit for switched mode power supply |
US7372682B2 (en) * | 2004-02-12 | 2008-05-13 | Power-One, Inc. | System and method for managing fault in a power system |
US7176714B1 (en) * | 2004-05-27 | 2007-02-13 | Altera Corporation | Multiple data rate memory interface architecture |
US20050286709A1 (en) * | 2004-06-28 | 2005-12-29 | Steve Horton | Customer service marketing |
KR100713082B1 (ko) * | 2005-03-02 | 2007-05-02 | 주식회사 하이닉스반도체 | 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프 |
US7141956B2 (en) * | 2005-03-18 | 2006-11-28 | Power-One, Inc. | Digital output voltage regulation circuit having first control loop for high speed and second control loop for high accuracy |
US7554310B2 (en) * | 2005-03-18 | 2009-06-30 | Power-One, Inc. | Digital double-loop output voltage regulation |
US7239115B2 (en) * | 2005-04-04 | 2007-07-03 | Power-One, Inc. | Digital pulse width modulation controller with preset filter coefficients |
US7327149B2 (en) * | 2005-05-10 | 2008-02-05 | Power-One, Inc. | Bi-directional MOS current sense circuit |
KR100757921B1 (ko) * | 2006-03-07 | 2007-09-11 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 dll 회로 및 클럭 지연 고정 방법 |
KR100779381B1 (ko) * | 2006-05-15 | 2007-11-23 | 주식회사 하이닉스반도체 | 감소된 면적을 가지는 dll과 이를 포함하는 반도체메모리 장치 및 그 락킹 동작 방법 |
US7834613B2 (en) * | 2007-10-30 | 2010-11-16 | Power-One, Inc. | Isolated current to voltage, voltage to voltage converter |
KR101018690B1 (ko) * | 2008-10-31 | 2011-03-04 | 주식회사 하이닉스반도체 | 반도체 장치 |
US8451042B2 (en) | 2011-06-03 | 2013-05-28 | Texas Instruments Incorporated | Apparatus and system of implementation of digital phase interpolator with improved linearity |
KR101771980B1 (ko) * | 2011-10-20 | 2017-08-30 | 에스케이하이닉스 주식회사 | 위상 혼합 회로 및 이를 포함하는 지연고정루프 |
US8791737B2 (en) * | 2012-08-20 | 2014-07-29 | Nanya Technology Corporation | Phase-locked loop and method for clock delay adjustment |
CN106502298B (zh) * | 2016-12-20 | 2017-11-14 | 中国电子科技集团公司第五十八研究所 | 一种应用于低压相位内插器中电流产生电路 |
CN107888166B (zh) * | 2017-11-30 | 2021-11-05 | 北京大学深圳研究生院 | 多相位不交叠时钟信号产生电路及相应的方法 |
KR20220036175A (ko) | 2020-09-15 | 2022-03-22 | 삼성전자주식회사 | 메모리 장치 및 그것의 클록 라킹 방법 |
CN112910459B (zh) * | 2021-01-29 | 2022-05-17 | 华中科技大学 | 一种用于产生四相延时信号的方法及dll电路 |
CN115549655A (zh) * | 2021-06-29 | 2022-12-30 | 澜起电子科技(昆山)有限公司 | 延迟装置及延迟控制方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5457718A (en) * | 1992-03-02 | 1995-10-10 | International Business Machines Corporation | Compact phase recovery scheme using digital circuits |
US6028488A (en) * | 1996-11-08 | 2000-02-22 | Texas Instruments Incorporated | Digitally-controlled oscillator with switched-capacitor frequency selection |
US6115439A (en) * | 1997-11-14 | 2000-09-05 | Texas Instruments Incorporated | Free running digital phase lock loop |
JP3789247B2 (ja) * | 1999-02-26 | 2006-06-21 | Necエレクトロニクス株式会社 | クロック周期検知回路 |
JP2001007698A (ja) * | 1999-06-25 | 2001-01-12 | Mitsubishi Electric Corp | データpll回路 |
JP3647364B2 (ja) * | 2000-07-21 | 2005-05-11 | Necエレクトロニクス株式会社 | クロック制御方法及び回路 |
JP3636657B2 (ja) * | 2000-12-21 | 2005-04-06 | Necエレクトロニクス株式会社 | クロックアンドデータリカバリ回路とそのクロック制御方法 |
KR100417858B1 (ko) * | 2001-07-27 | 2004-02-05 | 주식회사 하이닉스반도체 | 저전력형 램버스 디램 |
KR100424181B1 (ko) * | 2001-12-21 | 2004-03-24 | 주식회사 하이닉스반도체 | 제어된 타이밍을 갖는 출력 클록 신호를 생성하는 회로 및방법 |
KR100477809B1 (ko) * | 2002-05-21 | 2005-03-21 | 주식회사 하이닉스반도체 | 듀티 사이클 교정이 가능한 디지털 디엘엘 장치 및 듀티사이클 교정 방법 |
-
2003
- 2003-10-30 US US10/696,920 patent/US20050093594A1/en not_active Abandoned
-
2004
- 2004-09-30 EP EP04787070A patent/EP1634375B1/de not_active Expired - Fee Related
- 2004-09-30 KR KR1020067008287A patent/KR100817962B1/ko not_active IP Right Cessation
- 2004-09-30 DE DE602004004533T patent/DE602004004533T2/de not_active Expired - Fee Related
- 2004-09-30 WO PCT/EP2004/010941 patent/WO2005048455A1/en active IP Right Grant
- 2004-09-30 CN CNA2004800249381A patent/CN1846355A/zh active Pending
- 2004-09-30 JP JP2006523003A patent/JP2007502067A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
KR100817962B1 (ko) | 2008-03-31 |
US20050093594A1 (en) | 2005-05-05 |
EP1634375B1 (de) | 2007-01-24 |
KR20060067976A (ko) | 2006-06-20 |
WO2005048455A1 (en) | 2005-05-26 |
CN1846355A (zh) | 2006-10-11 |
JP2007502067A (ja) | 2007-02-01 |
EP1634375A1 (de) | 2006-03-15 |
DE602004004533T2 (de) | 2007-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |