DE60142568D1 - - Google Patents

Info

Publication number
DE60142568D1
DE60142568D1 DE60142568T DE60142568T DE60142568D1 DE 60142568 D1 DE60142568 D1 DE 60142568D1 DE 60142568 T DE60142568 T DE 60142568T DE 60142568 T DE60142568 T DE 60142568T DE 60142568 D1 DE60142568 D1 DE 60142568D1
Authority
DE
Germany
Prior art keywords
edges
adjusted
pulse
clock signals
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60142568T
Other languages
English (en)
Inventor
Frank W Singor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of DE60142568D1 publication Critical patent/DE60142568D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE60142568T 2000-08-03 2001-08-03 Expired - Lifetime DE60142568D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22311200P 2000-08-03 2000-08-03
US22416900P 2000-08-09 2000-08-09
PCT/US2001/041533 WO2002013201A2 (en) 2000-08-03 2001-08-03 Circuit and method for multi-phase alignment

Publications (1)

Publication Number Publication Date
DE60142568D1 true DE60142568D1 (de) 2010-08-26

Family

ID=26917454

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60142568T Expired - Lifetime DE60142568D1 (de) 2000-08-03 2001-08-03

Country Status (5)

Country Link
US (2) US6437620B1 (de)
EP (1) EP1316092B1 (de)
AT (1) ATE474317T1 (de)
DE (1) DE60142568D1 (de)
WO (1) WO2002013201A2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6744285B2 (en) * 2002-08-08 2004-06-01 Agilent Technologies, Inc. Method and apparatus for synchronously transferring data across multiple clock domains
JP3935139B2 (ja) 2002-11-29 2007-06-20 株式会社東芝 半導体記憶装置
JP4077337B2 (ja) * 2003-02-27 2008-04-16 株式会社東芝 パルス発生回路及びそれを用いたハイサイドドライバ回路
US6859109B1 (en) 2003-05-27 2005-02-22 Pericom Semiconductor Corp. Double-data rate phase-locked-loop with phase aligners to reduce clock skew
US9615061B2 (en) * 2003-07-11 2017-04-04 Tvworks, Llc System and method for creating and presenting composite video-on-demand content
US7552225B2 (en) * 2004-04-28 2009-06-23 International Business Machines Corporation Enhanced media resource protocol messages
CN100381968C (zh) * 2004-11-01 2008-04-16 联发科技股份有限公司 系统时钟脉冲切换装置以及切换其频率的方法
JP6476659B2 (ja) * 2014-08-28 2019-03-06 富士通株式会社 信号再生回路および信号再生方法
US10243460B2 (en) * 2017-02-28 2019-03-26 Infineon Technologies Austria Ag Method and apparatus for dynamic voltage transition control in semi-resonant and resonant converters

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137307A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd パルスカウントｆｍ検波回路
GB2157519A (en) * 1984-04-14 1985-10-23 Coorosh Sabet A sample and hold circuit
EP0433032A3 (en) * 1989-12-15 1992-08-05 Matsushita Electric Industrial Co., Ltd. Signal reproducing apparatus
US5638016A (en) 1995-04-18 1997-06-10 Cyrix Corporation Adjustable duty cycle clock generator
JP3054579B2 (ja) * 1995-05-25 2000-06-19 三洋電機株式会社 Ｖｔｒのイコライザ回路
US5675273A (en) 1995-09-08 1997-10-07 International Business Machines Corporation Clock regulator with precision midcycle edge timing
JP2000013204A (ja) * 1998-06-18 2000-01-14 Fujitsu Ltd 遅延回路及び該遅延回路を用いた発振回路

Also Published As

Publication number Publication date
EP1316092A2 (de) 2003-06-04
US20020021154A1 (en) 2002-02-21
ATE474317T1 (de) 2010-07-15
US6525580B2 (en) 2003-02-25
EP1316092B1 (de) 2010-07-14
WO2002013201A2 (en) 2002-02-14
WO2002013201A3 (en) 2002-05-10
US20020153930A1 (en) 2002-10-24
US6437620B1 (en) 2002-08-20

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