GB2157519A

GB2157519A - A sample and hold circuit

Info

Publication number: GB2157519A
Application number: GB08409781A
Authority: GB
Inventors: Coorosh Sabet
Original assignee: Individual
Current assignee: Individual
Priority date: 1984-04-14
Filing date: 1984-04-14
Publication date: 1985-10-23

Abstract

A sample and hold circuit consists of three gates (1, 2, 5) such as Metal Oxide Silicon Field Effect Transistors or high speed diode bridges, two high input impedance buffers (4, 7) and two capacitors (3, 6) connected in cascade. A pulse conditioner/delay line provides three pulses A, B and C with predetermined delays between pulses A and B. In one embodiment gates 1 and 5 which are normally closed are opened on the simultaneous application of pulses A and C respectively. Gate 2 which is normally open is closed on the application of pulse B after a delay of DELTA t. The time delay DELTA t between opening gate 1 and closing gate 2 allows a sample of analogue input signal to pass through and be temporarily stored in capacitor 3. Meanwhile gate 3 allows the above-mentioned analogue sample to be stored for a sufficiently longer time in capacitor 6 in order to be digitized by the subsequent analogue to digital converter. Therefore the resolution of the present sample and hold circuit is substantially determined by the delay DELTA t which can be as short as required. <IMAGE>

Description

SPECIFICATION A sample and hold circuit This invention relates to a sample and hold circuit which can be used in numerous applications such as analogue to digital conversion, transient recording and digital storage oscilloscopes.

Sample and hold circuits are used for descretization of analogue waveforms. In the simplest form a sample and hold circuit consists of a gate and a storage device. The gate opens on application of a pulse and stays open for a period of time equal to the width of the applied pulse. The resolution of a sample and hold circuit is dependent, in addition to other factors, on the time during which the gate is open allowing a sample of the analogue signal to pass through it and subsequently be stored.

For high frequency application the abovementioned time interval becomes critical and the resolution is then determined by the speed at which the gate can open and subsequently close.

According to the present invention a sample and hold circuit is provided, the resolution of which is substantially independent of the speed at which an individual sampling gate opens and subsequently closes. Referring now to Figures 1 and 2, the sample and hold circuit according to the present invention consists of three gates such as Metal Oxide Silicon Field Effect Transistors or high speed diode bridges, two high input impedance buffers and two charge storage devices.

In quiescent mode, in the first embodiment, the first gate 1 (Fig. 1) is normally closed, the second gate 2 (Fig. 1) is normally open and the third gate 5 (Fig. 1) is normally closed.

In operation on application of pulse A (Fig. 2) gate 1 (Fig. 1) opens; after a delay At a second pulse B (Fig. 2) closes the gate 2 (Fig. 1). A third pulse C (Fig.

2) which is applied at the same time as pulse A (Fig.

2) opens the gate 3 (Fig. 1). Figure 2 illustrates the timing diagram of the controlling pulses. The action of gate 1 and gate 2 allows a sample of the analogue input signal to pass through and be stored in the capacitor 3 (Fig. 1). This action is termed in this invention the "SABET Slamming Action" (SSA) and the circuit is called here the "SABET Slamming Sampling Gates" (SSSG).

The duration of the pulse C (Fig. 2) should be long enough for the capacitor 6 (Fig. 1 ) to become fully charged. The size of the capacitor 6 (Fig. 1) and the input impedance of the buffer 7 (Fig. 1) are determined by the speed at which the subsequent analogue to digital convertor 8 (Fig. 1) is operating.

The duration of At which is determined by the delay between pulse A and pulse B can be adjusted to any value. Depending on the transition edge of the controlling pulses the situation in Figure 3 can arise in which case the attenuating effect of the combined SSA becomes larger and larger as At becomes smaller. This attenuation can, however, be compensated to a certain extent by suitable preamplification of the analogue input signal.

It can therefore be seen that the resolution of the present sample and hold circuit substantially depends on the time delay Zit between opening gate 1 and closing gate 2 and this can practically be as small as required. The resolution depends also to a certain extent on the slopes of the transition edges of pulses A and B or the switching-time of gate 1 and 2 whichever the longer. As far as practicable it is immaterial how long the individual gates remain in the transition stage; in other words, the widths of pulses A and B do not determine the resolution of the SSSG.

In a second embodiment the switching configuration of SSSG can be reversed such that in the quiescent state gate 1 (Fig. 1) is open, gate 2 (Fig.

1) is closed and gate 3 (Fig. 1) is closed. The action of pulses A, B and C with suitable polarity would now be to open gates 2 and 3 simultaneously and close gate 1 after a delay At. A similar argument as that given for the first embodiment applies regarding the widths of pulses A, B and C. In a second embodiment the gates 1 and 2 can be replaced by a single device such as a dual insulated gate Metal Oxide Silicon Field Effect Transistor.

Claims

1. A sample and hold circuit (shown in Figure 1) comprising 3 gates such as Metal Oxide Field Effect Transistors, 2 capacitors, 2 high input impedance buffers and a pulse conditioner/delay line.

2. A sample and hold circuit according to claim 1 wherein a pulse conditioner provides three pulse A, B and C with predetermined rise-time, fall-time and rise-time respectively.

3. A sample and hold circuit according to claims 1 to 2 wherein a pulse conditioner provides pulses A and B with predetermined delays which substantially determine the resolution of the sample and hold circuit.

4. A sample and hold circuit according to claims 1 to 3 wherein buffers provide isolation between gates and storage devices.

5. A sample and hold circuit according to claims 1 to 4 wherein storage 3 and 6 are capacitors.

6. A sample and hold circuit according to claims 1 to 5 and as illustrated in Figures 1 to 3 wherein gate 1 is normally closed, gate 2 is normally open and gate 3 is normally closed. In operation, pulses A and C open gates 1 and 3 respectively and preferably simultaneously. After a delay At pulse B closes gate 2 hence allowing a predetermined size of the analogue input signal to pass through and be temporarily stored in capacitor 3 and subsequently stored in capacitor 6 for a longer time - long enough for the subsequent analogue to digital converter 8 to convert the analogue sample to digital sample.

7. A sample and hold circuit according to claims 1 to 5 and as illustrated in Figures 1 to 3 wherein gate 1 is normally open, gate 2 is normally closed and gate 3 is normally closed. In operation, pulses B and C open gates 2 and 3 respectively and preferably simultaneously. After a delay At pulse A closes gate 1 hence allowing a predetermined size of analogue input signal to pass through and be temporarily stored in capacitor 3 and subsequently stored in capacitor 6 for a longer time - long enough for the subsequent analogue to digital converter 8 to convert the analogue sample to digital sample.

8. A sample and hold circuit according to claims 1 to 7 wherein the resolution is primarily determined by the length of the delay time At between the application of pulse A and pulse B.

9. A sample and hold circuit substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.