DE60127357D1 - Ausführung von einem PCI-Arbiter mit dynamischem Prioritätsschema - Google Patents
Ausführung von einem PCI-Arbiter mit dynamischem PrioritätsschemaInfo
- Publication number
- DE60127357D1 DE60127357D1 DE60127357T DE60127357T DE60127357D1 DE 60127357 D1 DE60127357 D1 DE 60127357D1 DE 60127357 T DE60127357 T DE 60127357T DE 60127357 T DE60127357 T DE 60127357T DE 60127357 D1 DE60127357 D1 DE 60127357D1
- Authority
- DE
- Germany
- Prior art keywords
- execution
- priority scheme
- dynamic priority
- pci arbiter
- arbiter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US637846 | 1991-01-04 | ||
US09/637,846 US6826644B1 (en) | 2000-08-10 | 2000-08-10 | Peripheral component interconnect arbiter implementation with dynamic priority scheme |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60127357D1 true DE60127357D1 (de) | 2007-05-03 |
DE60127357T2 DE60127357T2 (de) | 2007-11-29 |
Family
ID=24557593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60127357T Expired - Lifetime DE60127357T2 (de) | 2000-08-10 | 2001-08-09 | Ausführung von einem PCI-Arbiter mit dynamischem Prioritätsschema |
Country Status (3)
Country | Link |
---|---|
US (2) | US6826644B1 (de) |
EP (1) | EP1187029B1 (de) |
DE (1) | DE60127357T2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW515960B (en) * | 2000-08-11 | 2003-01-01 | Via Tech Inc | Architecture and method of extended bus and bridge thereof |
US7062582B1 (en) | 2003-03-14 | 2006-06-13 | Marvell International Ltd. | Method and apparatus for bus arbitration dynamic priority based on waiting period |
US7321947B2 (en) * | 2005-03-10 | 2008-01-22 | Dell Products L.P. | Systems and methods for managing multiple hot plug operations |
US7404025B2 (en) * | 2005-04-14 | 2008-07-22 | Texas Instruments Incorporated | Software programmable dynamically reconfigurable scheme for controlling request grant and masking for ultra high priority accessor during arbitration |
US7380040B2 (en) * | 2005-04-14 | 2008-05-27 | Texas Instruments Incorporated | Software programmable dynamic arbitration scheme |
JP2010140440A (ja) * | 2008-12-15 | 2010-06-24 | Toshiba Corp | バス調停装置 |
JP2014016730A (ja) * | 2012-07-06 | 2014-01-30 | Canon Inc | バス調停装置、バス調停方法、及びコンピュータプログラム |
US9684633B2 (en) * | 2013-01-24 | 2017-06-20 | Samsung Electronics Co., Ltd. | Adaptive service controller, system on chip and method of controlling the same |
US9471524B2 (en) | 2013-12-09 | 2016-10-18 | Atmel Corporation | System bus transaction queue reallocation |
CN110502461B (zh) * | 2019-08-27 | 2023-03-24 | 深圳市中物互联技术发展有限公司 | 一种基于rs485通讯协议的高效数据采集方法 |
CN110674065B (zh) * | 2019-10-09 | 2021-01-15 | 上海钧正网络科技有限公司 | 一种在总线上的竞争仲裁方法和系统 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5848297A (en) * | 1991-12-30 | 1998-12-08 | Apple Computer, Inc. | Control apparatus for maintaining order and accomplishing priority promotion in a computer interconnect |
US5640599A (en) * | 1991-12-30 | 1997-06-17 | Apple Computer, Inc. | Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed |
US5592631A (en) * | 1995-05-02 | 1997-01-07 | Apple Computer, Inc. | Bus transaction reordering using side-band information signals |
US5850530A (en) * | 1995-12-18 | 1998-12-15 | International Business Machines Corporation | Method and apparatus for improving bus efficiency by enabling arbitration based upon availability of completion data |
KR0167726B1 (ko) * | 1996-01-30 | 1999-01-15 | 김광호 | 버스의 우선권 선택장치 |
US5930487A (en) * | 1996-03-06 | 1999-07-27 | Vlsi Technology, Inc. | PCI bus master with cascaded PCI arbitration |
US5761452A (en) | 1996-03-18 | 1998-06-02 | Advanced Micro Devices, Inc. | Bus arbiter method and system |
US5933610A (en) * | 1996-09-17 | 1999-08-03 | Vlsi Technology, Inc. | Predictive arbitration system for PCI bus agents |
US6141715A (en) * | 1997-04-03 | 2000-10-31 | Micron Technology, Inc. | Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction |
US5872937A (en) * | 1997-04-17 | 1999-02-16 | Vlsi Technology, Inc. | System for optimizing bus arbitration latency and method therefor |
US6178477B1 (en) * | 1997-10-09 | 2001-01-23 | Vlsi Technology, Inc. | Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource |
US5987555A (en) * | 1997-12-22 | 1999-11-16 | Compaq Computer Corporation | Dynamic delayed transaction discard counter in a bus bridge of a computer system |
US6199127B1 (en) * | 1997-12-24 | 2001-03-06 | Intel Corporation | Method and apparatus for throttling high priority memory accesses |
US6393506B1 (en) * | 1999-06-15 | 2002-05-21 | National Semiconductor Corporation | Virtual channel bus and system architecture |
US6499090B1 (en) * | 1999-12-28 | 2002-12-24 | Intel Corporation | Prioritized bus request scheduling mechanism for processing devices |
-
2000
- 2000-08-10 US US09/637,846 patent/US6826644B1/en not_active Expired - Lifetime
-
2001
- 2001-08-09 EP EP01250291A patent/EP1187029B1/de not_active Expired - Lifetime
- 2001-08-09 DE DE60127357T patent/DE60127357T2/de not_active Expired - Lifetime
-
2004
- 2004-10-12 US US10/963,061 patent/US7234012B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1187029A2 (de) | 2002-03-13 |
US7234012B2 (en) | 2007-06-19 |
DE60127357T2 (de) | 2007-11-29 |
EP1187029B1 (de) | 2007-03-21 |
US20050066094A1 (en) | 2005-03-24 |
EP1187029A3 (de) | 2003-11-05 |
US6826644B1 (en) | 2004-11-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M |