DE60127335T2 - Vorrichtung und Verfahren zum Schutz integrierter Ladungsspeicherelemente vor photoinduzierten Strömen - Google Patents

Vorrichtung und Verfahren zum Schutz integrierter Ladungsspeicherelemente vor photoinduzierten Strömen Download PDF

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Publication number
DE60127335T2
DE60127335T2 DE60127335T DE60127335T DE60127335T2 DE 60127335 T2 DE60127335 T2 DE 60127335T2 DE 60127335 T DE60127335 T DE 60127335T DE 60127335 T DE60127335 T DE 60127335T DE 60127335 T2 DE60127335 T2 DE 60127335T2
Authority
DE
Germany
Prior art keywords
storage node
light
circuit
node circuit
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60127335T
Other languages
German (de)
English (en)
Other versions
DE60127335D1 (de
Inventor
John J. Portola Valley Corcoran
Travis N. Charlottesville Blalock
Paul J. San Mateo Vande Voorde
Thomas A. Palo Alto Knotts
Neela B. Saratoga Gaddis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aptina Imaging Corp
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of DE60127335D1 publication Critical patent/DE60127335D1/de
Publication of DE60127335T2 publication Critical patent/DE60127335T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Liquid Crystal (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE60127335T 2000-03-30 2001-01-18 Vorrichtung und Verfahren zum Schutz integrierter Ladungsspeicherelemente vor photoinduzierten Strömen Expired - Lifetime DE60127335T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/539,490 US6586283B2 (en) 2000-03-30 2000-03-30 Apparatus and method for protecting integrated circuit charge storage elements from photo-induced currents
US539490 2000-03-30

Publications (2)

Publication Number Publication Date
DE60127335D1 DE60127335D1 (de) 2007-05-03
DE60127335T2 true DE60127335T2 (de) 2007-12-20

Family

ID=24151436

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60127335T Expired - Lifetime DE60127335T2 (de) 2000-03-30 2001-01-18 Vorrichtung und Verfahren zum Schutz integrierter Ladungsspeicherelemente vor photoinduzierten Strömen

Country Status (4)

Country Link
US (1) US6586283B2 (enExample)
EP (1) EP1139417B1 (enExample)
JP (1) JP2001352041A (enExample)
DE (1) DE60127335T2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552597B1 (en) * 2001-11-02 2003-04-22 Power Integrations, Inc. Integrated circuit with closely coupled high voltage output and offline transistor pair
US7194470B2 (en) 2002-06-19 2007-03-20 Matsushita Electric Industrial Co., Ltd. Data delivery management system
US20060086974A1 (en) * 2004-10-26 2006-04-27 Power Integrations, Inc. Integrated circuit with multi-length power transistor segments
US7135748B2 (en) * 2004-10-26 2006-11-14 Power Integrations, Inc. Integrated circuit with multi-length output transistor segment
TW202439593A (zh) * 2023-03-20 2024-10-01 聯華電子股份有限公司 半導體元件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279787A (en) * 1975-12-26 1977-07-05 Toshiba Corp Integrated circuit device
US4597805A (en) * 1979-10-11 1986-07-01 Texas Instruments Incorporated Making guard ring for reducing pattern sensitivity in MOS/LSI dynamic RAM
FR2481553A1 (fr) * 1980-04-23 1981-10-30 Thomson Csf Dispositif photosensible lu par transfert de charges et camera de television comportant un tel dispositif
JPS60140862A (ja) * 1983-12-28 1985-07-25 Nec Corp 半導体記憶装置
JPS62117361A (ja) * 1985-11-15 1987-05-28 Mitsubishi Electric Corp 半導体メモリ装置
JPS62298105A (ja) * 1986-06-18 1987-12-25 Hitachi Micro Comput Eng Ltd 半導体集積回路装置
JPH01309354A (ja) * 1988-06-07 1989-12-13 Nec Corp 半導体集積回路
JPH0316156A (ja) * 1989-06-14 1991-01-24 Nissan Motor Co Ltd 半導体装置
JPH04316362A (ja) * 1991-04-15 1992-11-06 Sony Corp 半導体装置
JP3075892B2 (ja) * 1993-07-09 2000-08-14 株式会社東芝 半導体装置
US5614744A (en) * 1995-08-04 1997-03-25 National Semiconductor Corporation CMOS-based, low leakage active pixel array with anti-blooming isolation
JP3669098B2 (ja) * 1997-02-14 2005-07-06 株式会社ニコン 半導体集積回路の容量
JP4140071B2 (ja) * 1997-11-04 2008-08-27 沖電気工業株式会社 半導体集積回路、半導体集積回路のレイアウト方法およびレイアウト装置
US6066883A (en) * 1998-03-16 2000-05-23 Xerox Corporation Guarding for a CMOS photosensor chip
US6218692B1 (en) * 1999-11-23 2001-04-17 Eastman Kodak Company Color active pixel sensor with electronic shuttering, anti-blooming and low cross talk

Also Published As

Publication number Publication date
US6586283B2 (en) 2003-07-01
JP2001352041A (ja) 2001-12-21
EP1139417B1 (en) 2007-03-21
EP1139417A2 (en) 2001-10-04
US20030075770A1 (en) 2003-04-24
DE60127335D1 (de) 2007-05-03
EP1139417A3 (en) 2004-07-14

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: MICRON TECHNOLOGY, INC., BOISE, ID., US

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: APTINA IMAGING CORP., GRAND CAYMAN, CAYMAN ISL, KY