DE60118622D1 - Benutzer-konfigurierbares on-chip speichersystem - Google Patents

Benutzer-konfigurierbares on-chip speichersystem

Info

Publication number
DE60118622D1
DE60118622D1 DE60118622T DE60118622T DE60118622D1 DE 60118622 D1 DE60118622 D1 DE 60118622D1 DE 60118622 T DE60118622 T DE 60118622T DE 60118622 T DE60118622 T DE 60118622T DE 60118622 D1 DE60118622 D1 DE 60118622D1
Authority
DE
Germany
Prior art keywords
storage system
chip storage
user configurable
configurable
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60118622T
Other languages
English (en)
Other versions
DE60118622T2 (de
Inventor
R Ansari
M Douglass
R Vashi
P Young
L Sastry
Robert Yin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/757,760 external-priority patent/US6522167B1/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60118622D1 publication Critical patent/DE60118622D1/de
Publication of DE60118622T2 publication Critical patent/DE60118622T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)
  • Advance Control (AREA)
DE60118622T 2001-01-09 2001-12-10 Benutzer-konfigurierbares on-chip speichersystem Expired - Lifetime DE60118622T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US757760 1991-09-11
US09/757,760 US6522167B1 (en) 2001-01-09 2001-01-09 User configurable on-chip memory system
US917304 2001-07-27
US09/917,304 US6662285B1 (en) 2001-01-09 2001-07-27 User configurable memory system having local and global memory blocks
PCT/US2001/047743 WO2002056180A2 (en) 2001-01-09 2001-12-10 User configurable on-chip memory system

Publications (2)

Publication Number Publication Date
DE60118622D1 true DE60118622D1 (de) 2006-05-18
DE60118622T2 DE60118622T2 (de) 2007-04-05

Family

ID=27116447

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60118622T Expired - Lifetime DE60118622T2 (de) 2001-01-09 2001-12-10 Benutzer-konfigurierbares on-chip speichersystem

Country Status (6)

Country Link
US (1) US6662285B1 (de)
EP (1) EP1386247B1 (de)
JP (1) JP3853736B2 (de)
CA (1) CA2434031C (de)
DE (1) DE60118622T2 (de)
WO (1) WO2002056180A2 (de)

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US6492881B2 (en) * 2001-01-31 2002-12-10 Compaq Information Technologies Group, L.P. Single to differential logic level interface for computer systems
US6605962B2 (en) 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US7420392B2 (en) * 2001-09-28 2008-09-02 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6934922B1 (en) 2002-02-27 2005-08-23 Xilinx, Inc. Timing performance analysis
US7085973B1 (en) 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
JP3970716B2 (ja) * 2002-08-05 2007-09-05 松下電器産業株式会社 半導体記憶装置およびその検査方法
US20040136241A1 (en) * 2002-10-31 2004-07-15 Lockheed Martin Corporation Pipeline accelerator for improved computing architecture and related system and method
US6803786B1 (en) 2003-03-11 2004-10-12 Xilinx, Inc. Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
US7421014B2 (en) * 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
US7885320B1 (en) 2003-09-11 2011-02-08 Xilinx, Inc. MGT/FPGA clock management system
JP4815570B2 (ja) * 2004-03-10 2011-11-16 エスティー‐エリクソン、ソシエテ、アノニム メモリアクセスを制御する方法及び集積回路
US7535759B2 (en) * 2004-06-04 2009-05-19 Micron Technology, Inc. Memory system with user configurable density/performance option
US8082382B2 (en) * 2004-06-04 2011-12-20 Micron Technology, Inc. Memory device with user configurable density/performance
JP4451733B2 (ja) 2004-06-30 2010-04-14 富士通マイクロエレクトロニクス株式会社 半導体装置
US7200693B2 (en) 2004-08-27 2007-04-03 Micron Technology, Inc. Memory system and method having unidirectional data buses
US7624209B1 (en) 2004-09-15 2009-11-24 Xilinx, Inc. Method of and circuit for enabling variable latency data transfers
WO2006039710A2 (en) * 2004-10-01 2006-04-13 Lockheed Martin Corporation Computer-based tool and method for designing an electronic circuit and related system and library for same
US20060136606A1 (en) * 2004-11-19 2006-06-22 Guzy D J Logic device comprising reconfigurable core logic for use in conjunction with microprocessor-based computer systems
US7209405B2 (en) 2005-02-23 2007-04-24 Micron Technology, Inc. Memory device and method having multiple internal data buses and memory bank interleaving
US20070028027A1 (en) * 2005-07-26 2007-02-01 Micron Technology, Inc. Memory device and method having separate write data and read data buses
US7711907B1 (en) * 2007-02-14 2010-05-04 Xilinx, Inc. Self aligning state machine
US7913022B1 (en) * 2007-02-14 2011-03-22 Xilinx, Inc. Port interface modules (PIMs) in a multi-port memory controller (MPMC)
US7720636B1 (en) 2007-02-14 2010-05-18 Xilinx, Inc. Performance monitors (PMs) for measuring performance in a system and providing a record of transactions performed
US8479124B1 (en) 2007-02-14 2013-07-02 Xilinx, Inc. Graphical user interface (GUI) including input files with information that determines representation of subsequent content displayed by the GUI
US7460398B1 (en) * 2007-06-19 2008-12-02 Micron Technology, Inc. Programming a memory with varying bits per cell
US8407400B2 (en) * 2008-11-12 2013-03-26 Micron Technology, Inc. Dynamic SLC/MLC blocks allocations for non-volatile memory
US8813018B1 (en) * 2012-10-05 2014-08-19 Altera Corporation Method and apparatus for automatically configuring memory size
US10657067B1 (en) 2016-09-12 2020-05-19 Xilinx, Inc. Memory management unit with prefetch
US10754993B2 (en) * 2018-09-25 2020-08-25 Northrop Grumman Systems Corporation Architecture to mitigate configuration memory imprinting in programmable logic
KR20210025403A (ko) 2019-08-27 2021-03-09 삼성전자주식회사 무선 통신 시스템에서 다중 fpga를 운영하기 위한 장치 및 방법
EP4198750A1 (de) * 2021-12-17 2023-06-21 dSPACE GmbH Verfahren zur datenkommunikation zwischen teilbereichen eines fpgas

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US5072418A (en) * 1989-05-04 1991-12-10 Texas Instruments Incorporated Series maxium/minimum function computing devices, systems and methods
JPH02235156A (ja) * 1989-03-08 1990-09-18 Canon Inc 情報処理装置
JPH03210649A (ja) * 1990-01-12 1991-09-13 Fujitsu Ltd マイクロコンピュータおよびそのバスサイクル制御方法
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5671355A (en) 1992-06-26 1997-09-23 Predacomm, Inc. Reconfigurable network interface apparatus and method
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
JPH0736858A (ja) 1993-07-21 1995-02-07 Hitachi Ltd 信号処理プロセッサ
WO1995004402A1 (en) 1993-08-03 1995-02-09 Xilinx, Inc. Microprocessor-based fpga
US5740404A (en) * 1993-09-27 1998-04-14 Hitachi America Limited Digital signal processor with on-chip select decoder and wait state generator
US5732250A (en) * 1994-09-15 1998-03-24 Intel Corporation Multi-function microprocessor wait state mechanism using external control line
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5752035A (en) 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5933023A (en) 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US5914616A (en) 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US6011407A (en) * 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US5995424A (en) * 1997-07-16 1999-11-30 Tanisys Technology, Inc. Synchronous memory test system
US6020755A (en) 1997-09-26 2000-02-01 Lucent Technologies Inc. Hybrid programmable gate arrays
US6279045B1 (en) 1997-12-29 2001-08-21 Kawasaki Steel Corporation Multimedia interface having a multimedia processor and a field programmable gate array
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6343207B1 (en) 1998-11-03 2002-01-29 Harris Corporation Field programmable radio frequency communications equipment including a configurable if circuit, and method therefor
US6356987B1 (en) * 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states

Also Published As

Publication number Publication date
WO2002056180A3 (en) 2003-12-04
JP2004529403A (ja) 2004-09-24
US6662285B1 (en) 2003-12-09
EP1386247A2 (de) 2004-02-04
CA2434031A1 (en) 2002-07-18
JP3853736B2 (ja) 2006-12-06
WO2002056180A2 (en) 2002-07-18
CA2434031C (en) 2007-06-19
DE60118622T2 (de) 2007-04-05
EP1386247B1 (de) 2006-04-05

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Legal Events

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