DE60116975D1 - Semiconductor memory device and data processing unit - Google Patents

Semiconductor memory device and data processing unit

Info

Publication number
DE60116975D1
DE60116975D1 DE60116975T DE60116975T DE60116975D1 DE 60116975 D1 DE60116975 D1 DE 60116975D1 DE 60116975 T DE60116975 T DE 60116975T DE 60116975 T DE60116975 T DE 60116975T DE 60116975 D1 DE60116975 D1 DE 60116975D1
Authority
DE
Germany
Prior art keywords
processing unit
data processing
memory device
semiconductor memory
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60116975T
Other languages
German (de)
Other versions
DE60116975T2 (en
Inventor
Toshiya Uchida
Shusaku Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001045545A external-priority patent/JP4651206B2/en
Priority claimed from JP2001048653A external-priority patent/JP5226161B2/en
Priority claimed from JP2001054567A external-priority patent/JP4772975B2/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60116975D1 publication Critical patent/DE60116975D1/en
Publication of DE60116975T2 publication Critical patent/DE60116975T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
DE60116975T 2001-02-21 2001-11-29 Semiconductor memory device and data processing unit Expired - Lifetime DE60116975T2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2001045545 2001-02-21
JP2001045545A JP4651206B2 (en) 2001-02-21 2001-02-21 Semiconductor memory device and information processing apparatus
JP2001048653A JP5226161B2 (en) 2001-02-23 2001-02-23 Semiconductor memory device and information processing system
JP2001048653 2001-02-23
JP2001054567 2001-02-28
JP2001054567A JP4772975B2 (en) 2001-02-28 2001-02-28 Semiconductor memory device

Publications (2)

Publication Number Publication Date
DE60116975D1 true DE60116975D1 (en) 2006-04-13
DE60116975T2 DE60116975T2 (en) 2006-07-27

Family

ID=27346055

Family Applications (3)

Application Number Title Priority Date Filing Date
DE60122025T Expired - Lifetime DE60122025T2 (en) 2001-02-21 2001-11-29 Semiconductor memory device and data processing unit
DE60116975T Expired - Lifetime DE60116975T2 (en) 2001-02-21 2001-11-29 Semiconductor memory device and data processing unit
DE60132829T Expired - Lifetime DE60132829T2 (en) 2001-02-21 2001-11-29 Semiconductor memory device and data processing unit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE60122025T Expired - Lifetime DE60122025T2 (en) 2001-02-21 2001-11-29 Semiconductor memory device and data processing unit

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60132829T Expired - Lifetime DE60132829T2 (en) 2001-02-21 2001-11-29 Semiconductor memory device and data processing unit

Country Status (6)

Country Link
US (1) US6545942B2 (en)
EP (3) EP1486877B1 (en)
KR (1) KR100708558B1 (en)
CN (2) CN100536022C (en)
DE (3) DE60122025T2 (en)
TW (1) TWI231903B (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4078119B2 (en) * 2002-04-15 2008-04-23 富士通株式会社 Semiconductor memory
JP2004246525A (en) * 2003-02-13 2004-09-02 Matsushita Electric Ind Co Ltd Sequence circuit, storage element, clock generation circuit and clock control method, circuit changing method and circuit design support device, semiconductor integrated circuit and electronic device with it, electronic control device and mobile body with it
US7191162B2 (en) * 2003-10-21 2007-03-13 Texas Instruments Incorporated FIFO interface for flag-initiated DMA frame synchro-burst operation
KR100809690B1 (en) * 2006-07-14 2008-03-07 삼성전자주식회사 Semiconductor memory device capable of low frequency test operation and test method of the same
TWI425354B (en) 2007-10-16 2014-02-01 Mstar Semiconductor Inc Data access system and method
CN101419599B (en) * 2007-10-25 2013-03-13 晨星半导体股份有限公司 Data access system and method
KR101507122B1 (en) 2008-04-29 2015-04-01 삼성전자주식회사 Semiconductor memory device and access method thereof
US20110238870A1 (en) * 2008-12-03 2011-09-29 Rambus Inc. Memory System With Command Filtering
US20100274933A1 (en) * 2009-04-24 2010-10-28 Mediatek Inc. Method and apparatus for reducing memory size and bandwidth
CN102486757B (en) * 2010-12-06 2016-09-28 群联电子股份有限公司 The method of memorizer memory devices and Memory Controller thereof and response host command
KR20130046122A (en) * 2011-10-27 2013-05-07 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
CN104281416B (en) * 2014-10-17 2017-09-01 北京海思敏医疗技术有限公司 Data acquisition, read method and device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0122099B1 (en) * 1994-03-03 1997-11-26 김광호 Synchronous semiconductor memory device having write latency control function
WO1997002571A1 (en) * 1995-06-30 1997-01-23 Micron Technologies, Inc. Distributed write data drivers for burst memories
JP2817679B2 (en) * 1995-09-20 1998-10-30 日本電気株式会社 Semiconductor memory
US5587961A (en) * 1996-02-16 1996-12-24 Micron Technology, Inc. Synchronous memory allowing early read command in write to read transitions
JP3238076B2 (en) * 1996-08-30 2001-12-10 株式会社東芝 Counter circuit and semiconductor memory device provided with this counter circuit
US5901304A (en) * 1997-03-13 1999-05-04 International Business Machines Corporation Emulating quasi-synchronous DRAM with asynchronous DRAM
US6172935B1 (en) * 1997-04-25 2001-01-09 Micron Technology, Inc. Synchronous dynamic random access memory device
US6192002B1 (en) * 1998-08-28 2001-02-20 Micron Technology Memory device with command buffer
JP2000148580A (en) * 1998-11-09 2000-05-30 Nec Corp Semiconductor storage device
JP3957421B2 (en) 1999-02-10 2007-08-15 エルピーダメモリ株式会社 Semiconductor memory device
EP1073064A1 (en) * 1999-07-30 2001-01-31 STMicroelectronics S.r.l. Non-volatile memory with the functional capability of simultaneous modification of the contents and burst mode read or page mode read
JP3416083B2 (en) * 1999-08-31 2003-06-16 株式会社日立製作所 Semiconductor device

Also Published As

Publication number Publication date
EP1486877A2 (en) 2004-12-15
US20020114210A1 (en) 2002-08-22
CN1372202A (en) 2002-10-02
EP1486877B1 (en) 2006-08-02
CN1530961A (en) 2004-09-22
EP1486878B1 (en) 2008-02-13
CN1202483C (en) 2005-05-18
EP1235155A2 (en) 2002-08-28
EP1235155B1 (en) 2006-02-01
TWI231903B (en) 2005-05-01
KR20020068454A (en) 2002-08-27
DE60122025T2 (en) 2006-11-23
DE60132829D1 (en) 2008-03-27
DE60116975T2 (en) 2006-07-27
EP1486878A3 (en) 2005-09-21
DE60122025D1 (en) 2006-09-14
CN100536022C (en) 2009-09-02
EP1235155A3 (en) 2003-11-05
KR100708558B1 (en) 2007-04-19
EP1486878A2 (en) 2004-12-15
DE60132829T2 (en) 2009-02-12
EP1486877A3 (en) 2005-09-21
US6545942B2 (en) 2003-04-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE