CN102486757B - The method of memorizer memory devices and Memory Controller thereof and response host command - Google Patents
The method of memorizer memory devices and Memory Controller thereof and response host command Download PDFInfo
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- CN102486757B CN102486757B CN201010580878.9A CN201010580878A CN102486757B CN 102486757 B CN102486757 B CN 102486757B CN 201010580878 A CN201010580878 A CN 201010580878A CN 102486757 B CN102486757 B CN 102486757B
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Abstract
A kind of method that the invention discloses memorizer memory devices and Memory Controller thereof and response host command.This memorizer memory devices has fast storage wafer and buffer storage.The method includes the write instruction that Receiving Host system is assigned, it is judged that whether write instruction causes memorizer memory devices trigger data to move the execution of program.If the method also includes that write instruction does not cause memorizer memory devices trigger data to move the execution of program, then when the write data corresponding to write instruction are completely transmitted to buffer storage, the confirmation of corresponding write instruction is sent to host computer system.
Description
Technical field
The present invention relates to a kind of method responding host command, particularly relate to a kind of the method that performs
Memorizer memory devices and Memory Controller thereof.
Background technology
Digital camera, mobile phone and MP3 are the rapidest in growth over the years so that consumer pair
The demand storing media increases the most rapidly.Owing to fast storage (Flash Memory) has number
According to non-volatile, power saving, volume little with mechanical structure etc. characteristic, therefore be very suitable for as this kind of
The storage media of portable product.
For using the fast storage storage device as storage media, when host computer system will
Under write instruction up to storage device time, first by the buffer storage Receiving Host in storage device
System transfers (transfer) and come data.After pending data is completely transferred to buffer storage,
Storage device just starts the data being temporarily stored in buffer storage are stored in fast storage.And store
One confirmation can be returned back to host computer system when write instruction is finished by device, main to notify
Machine system can assign next instruction.
But, host computer system, need to be through one section etc. after receiving the confirmation information of self-storing mechanism
Treat the time that (about 40 microsecond (μ s)) just can assign new instruction.It is to say, in above-mentioned wait
Within time, storage device is in idle state.Accordingly, how to reduce storage device and be in idle
The time of state, to promote its efficiency processing host command, becomes caused by those skilled in the art
The target of power.
Summary of the invention
In view of this, the present invention provides a kind of method responding host command, it is possible to allow host computer system
Assign next instruction in advance, avoid the execution time overtime of next instruction simultaneously.
The present invention provides a kind of Memory Controller, it is possible to allows host computer system assign the next one in advance and refers to
Order, avoids the execution time overtime of next instruction simultaneously.
The present invention provides a kind of memorizer memory devices, it is possible to allow host computer system assign the next one in advance
Instruction, avoids the execution time overtime of next instruction simultaneously.
The present invention proposes a kind of method responding host command, be used for having fast storage wafer with
The memorizer memory devices of buffer storage.The method includes that the write that Receiving Host system is assigned refers to
Order, it is judged that whether write instruction causes memorizer memory devices trigger data to move the execution of program.
If it is not, then when the write data corresponding to write instruction are completely transmitted to buffer storage, will
The confirmation of corresponding write instruction is sent to host computer system.
From the point of view of another viewpoint, the present invention proposes a kind of Memory Controller, and it includes host computer system
Interface, memory interface, buffer storage, and memory management circuitry.Wherein, main frame system
System interface is in order to couple host computer system.Memory interface is in order to couple fast storage wafer.Storage
Device management circuit is coupled to host system interface, memory interface and buffer storage.Memorizer pipe
The write instruction that reason circuit is assigned in order to Receiving Host system, and judge whether write instruction triggers number
According to the execution moving program.If write instruction trigger data will not move the execution of program, memorizer
Management circuit is also in order to be completely transmitted to buffer-stored in the write data corresponding to write instruction
During device, the confirmation of corresponding write instruction is sent to host computer system.
From the point of view of another viewpoint, the present invention proposes a kind of memorizer memory devices, including adapter,
Fast storage wafer, and Memory Controller.Wherein adapter is to couple host computer system.
Memory Controller is coupled to fast storage wafer and adapter, and this Memory Controller includes one
Buffer storage.The write instruction that Memory Controller is assigned in order to Receiving Host system, and judge
Write instruction whether trigger data moves the execution of program.If write instruction will not trigger data be moved
The execution of program, Memory Controller also in order in the write data corresponding to write instruction by completely
When transmission is to buffer storage, the confirmation of corresponding write instruction is sent to host computer system.
Based on above-mentioned, the present invention is according to whether the write instruction from host computer system causes memorizer
Storage device trigger data moves the execution of program, to determine to return the confirmation of this write instruction
Reach the time point of host computer system.Accordingly, for being not result in the write instruction of data-moving program,
The information that will confirm that the most ahead of time before write instruction completes is sent to host computer system, and then allows host computer system
Next instruction can be assigned in advance.And for the write instruction of data-moving program can be caused, then etc.
Pending data just responds host computer system, to prevent the execution of next instruction after moving program finishes execution
Time overtime.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and
Accompanying drawing is coordinated to be described in detail below.
Accompanying drawing explanation
Figure 1A is according to the use memorizer memory devices depicted in the present invention one exemplary embodiment
The schematic diagram of host computer system.
Figure 1B is according to the computer depicted in the present invention one exemplary embodiment, input/output device
Schematic diagram with memorizer memory devices.
Fig. 1 C is to store up with memorizer according to the host computer system depicted in another exemplary embodiment of the present invention
The schematic diagram of cryopreservation device.
Fig. 2 is the summary block diagram of the memorizer memory devices shown in Figure 1A.
Fig. 3 is the summary side according to the Memory Controller depicted in the present invention one exemplary embodiment
Block diagram.
Fig. 4 is the time diagram that host computer system assigns two instructions.
Fig. 5 A, Fig. 5 B are according to the response host command depicted in the present invention one exemplary embodiment
The flow chart of method.
Main element symbol description:
1000: host computer system
1100: computer
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: portable disk
1214: storage card
1216: solid state hard disc
1310: digital camera
1312:SD card
1314:MMC card
1316: memory stick
1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: adapter
104: Memory Controller
106: fast storage wafer
1041: host system interface
1043: memory management circuitry
1045: buffer storage
1047: memory interface
3002: electric power management circuit
3004: error checking and correcting circuit
t1、t2、t3: time point
Tw: the waiting time
Tp: process the time
510～580,5001～5005: the response host command described in one embodiment of the invention
Each step of method
Detailed description of the invention
It is said that in general, memorizer memory devices (also referred to as, memory storage system) includes that memorizer is brilliant
Sheet and controller (also referred to as, control circuit).Being commonly stored device storage device can be together with host computer system
Use, so that host computer system can write data into memorizer memory devices or fill from memory storage
Put middle reading data.It addition, also having memorizer memory devices is to include in-line memory and can hold
Row in host computer system using substantially as the software of controller of this in-line memory.
Figure 1A is according to the use memorizer memory devices depicted in the present invention one exemplary embodiment
The schematic diagram of host computer system.
Host computer system 1000 includes computer 1100 and input/output (Input/Output, I/O)
Device 1106.Computer 1100 includes microprocessor 1102, random access memory (Random
Access Memory, RAM) 1104, system bus 1108 and data transmission interface 1110.
Input/output device 1106 includes mouse 1202 as shown in Figure 1B, keyboard 1204, display
1206 with printer 1208.It will be appreciated that the unrestricted input of device as shown in Figure 2 B/
Output device 1106, input/output device 1106 can also include other devices.
In exemplary embodiment of the present invention, memorizer memory devices 100 is to pass through data transmission interface
1110 couple with other elements of host computer system 1000.By microprocessor 1102, random access memory
Memorizer 1104 and the running of input/output device 1106, host computer system 1000 can be by data
Write is to memorizer memory devices 100, or reads data from memorizer memory devices 100.Example
As, memorizer memory devices 100 can be storage card 1214 as shown in Figure 1B, portable disk 1212,
Or solid state hard disc (Solid State Drive, SSD) 1216.
It is said that in general, host computer system 1000 is any system that can store data.Although at this model
In example embodiment, host computer system 1000 is to explain with computer system, but, in the present invention
In another exemplary embodiment, host computer system 1000 can also be mobile phone, digital camera, camera,
The systems such as communication device, audio player or video player.Such as, it is digital in host computer system
During camera 1310, the secure digital (Secure that memorizer memory devices is then used by it
Digital, SD) block 1312, multimedia storage (Multimedia Card, MMC) blocks 1314,
Memory stick (Memory Stick, MEM STICK) 1316, small-sized quickly (Compact Flash,
CF) card 1318 or embedded storage devices 1320 (as shown in Figure 1 C).Embedded storage device
1320 include embedded multi-media card (Embedded MMC, eMMC).It is noted that it is embedding
Entering formula multimedia card is to be coupled directly on the substrate of host computer system.
Fig. 2 is the block diagram of the memorizer memory devices 100 shown in Figure 1A.Refer to Fig. 2,
Memorizer memory devices 100 includes adapter 102, Memory Controller 104 and fast storage
Wafer 106.
Adapter 102 is coupled to Memory Controller 104, and in order to couple host computer system 1000.
In this exemplary embodiment, the coffret kind that adapter 102 is supported is serial advanced technology
Adnexa (Serial Advanced Technology Attachment, SATA) interface.But
In other exemplary embodiment, the coffret kind of adapter 102 can also be that general serial is total
Line (Universal Serial Bus, USB) interface, multimedia storage card (Multimedia Card,
MMC) interface, parallel Advanced Technology Attachment (Parallel Advanced Technology
Attachment, PATA) interface, Institute of Electrical and Electric Engineers (Institute of
Electrical and Electronic Engineers, IEEE) 1394 interfaces, high-speed peripheral
Component connecting interface (Peripheral Component Interconnect Express, PCI
Express), secure digital (Secure Digital, SD) interface, memory stick (Memory Stick,
MS) interface, small-sized quickly (Compact Flash, CF) interface, or integrate driving electronics
Any applicable interfaces such as (Integrated Drive Electronics, IDE) interface,
This is not any limitation as.
Memory Controller 104 can perform with hardware pattern or multiple logics of firmware pattern implementation
Lock or control instruction, and according to the instruction of host computer system 1000 in fast storage wafer 106
Carry out the write of data, read and operate with removing etc..Wherein, Memory Controller 104 is the most especially
In order to the method responding host command according to this exemplary embodiment, receiving host computer system 1000
Instruction after determine respond host computer system 1000 time.The response main frame of this exemplary embodiment refers to
The method of order will explain in rear cooperation accompanying drawing again.
Fast storage wafer 106 is coupled to Memory Controller 104.Fast storage wafer 106
It is to store such as file configuration table (File Allocation Table, FAT) or enhancement mode literary composition
The filesystem informations such as part system (New Technology File System, NTFS), and
Store data as general in word, image or audio files etc..For example, fast storage is brilliant
Sheet 106 is multilamellar memory cell (Multi Level Cell, MLC) NAND fast storage wafer,
But the invention is not restricted to this, fast storage wafer 106 can also be monolayer memory cell (Single
Level Cell, SLC) NAND fast storage wafer, other fast storage wafers or any
There is the memory chips of identical characteristics.
In this exemplary embodiment, fast storage wafer 106 is by several physical blocks
(block) being formed, each physical blocks includes multiple physical address (also referred to as entity respectively
The page), and can be independently written and concurrently disinfect corresponding to those physical page of same physical blocks.
In more detail, physical blocks is the least unit removed, when physical page is then for write data
Minimum unit.
Those physical blocks of fast storage wafer 106 can be logically grouped as system area
(system area), data field (data area), spare area (spare area) and take
For district (replacement area).Wherein, the physical blocks being grouped into system area is to store up
Deposit the relevant important information of memorizer memory devices 100, and the physical blocks being grouped into replacement district is
In order to replace the physical blocks damaged in data field or spare area.Therefore, at general access status
Under, host computer system 1000 also cannot access system area and the physical blocks replaced in district.It is grouped into
The physical blocks of data field can store the number that the write instruction assigned by host computer system 1000 is write
According to, and the physical blocks in spare area is in order to the reality in the replacement data district when performing write instruction
Body block.Such as, refer to when memorizer memory devices 100 receives the write of host computer system 1000
Order and when being intended to update (or write) data to a certain physical page of physical blocks a certain in data field,
Memory Controller 104 can extract a physical blocks from spare area and be intended to the entity being updated
Effective legacy data in block and the new data write to be write are to the entity extracted from spare area
In block, and will logically be associated as number written into the physical blocks of effective legacy data with new data
According to district, and the physical blocks to be updated in data field is purged and is logically associated as standby
Use district.The write instruction assigned in host computer system 1000 can cause in fast storage wafer 106
During merging (Merge) of the data of two physical blocks, namely this write instruction can cause memorizer
Storage device 100 triggers the execution of a data-moving program.In other words, memorizer memory devices 100
In Memory Controller 104 can perform this data-moving program.
Additionally, the number of purge of each physical blocks of fast storage wafer 106 is limited,
Such as physical blocks will be worn and torn after removing 10,000 times.Therefore cause quickly depositing when physical blocks abrasion
When the part storage volume loss of reservoir wafer 106 or performance significant degradation, can cause and be stored in it
In the loss of data, even cannot store the adverse effects such as data.In general, physical blocks
Abrasion depend on each physical blocks is stylized (program, or claim write) or remove
Number of times.Such as, identity logic block address is repeatedly used to write when host computer system 1000
During data, the block of the identical physical address caused in fast storage wafer 106 can be repeated
Ground write and removing, the abrasion of this physical blocks will be relatively high.
As long as it is said that in general, having block abrasion will reduce the performance of fast storage wafer 106.
In detail, in addition to the degeneration of the abrasion performance of block own, when unworn block is not enough to storage
During deposit data, the performance of fast storage wafer 106 entirety also can reduce.Therefore, when quickly depositing
When the quantity of block of wearing and tearing in reservoir wafer 106 is more than a threshold number, even if still having other blocks not
Abrasion, fast storage wafer 106 still can be judged as re-using.The most unworn
Block is considered to use the waste that will result in resource.
In order to increase the life-span of fast storage wafer 106, Memory Controller 104 can as far as possible
Use the block of fast storage wafer 106 fifty-fifty.For reaching the purpose averagely used, storage
Device controller 104 can carry out the data-moving running of exchange area block after access a period of time and come average
Abrasion (wear leveling).In other words, Memory Controller 104 is for average abrasion
Also a data-moving program can be performed.
Fig. 3 is the summary side according to the Memory Controller depicted in the present invention one exemplary embodiment
Block diagram.Refer to Fig. 3, Memory Controller 104 includes host system interface 1041, memorizer
Management circuit 1043, buffer storage 1045, and memory interface 1047.
Host system interface 1041 is coupled to memory management circuitry 1043, and by adapter 102
To couple host computer system 1000.Host system interface 1041 is to receive and identify host computer system
1000 instruction transmitted and data.Accordingly, host computer system 1000 is transmitted instruction and data
Memory management circuitry 1043 can be sent to by host system interface 1041.Real at this example
Execute in example, the corresponding adapter 102 of host system interface 1041 and be SATA interface, and at other
In exemplary embodiment, host system interface 1041 can also be USB interface, MMC interface, PATA
Interface, IEEE 1394 interface, PCI Express interface, SD interface, MS interface, CF interface,
Ide interface or meet the interface of other interface standards.
Memory management circuitry 1043 is to control the overall operation of Memory Controller 104.
Specifically, memory management circuitry 1043 has multiple control instruction, fills in memory storage
When putting 100 running, above-mentioned control instruction can be performed to realize the response main frame of this exemplary embodiment
The method of instruction.
In an exemplary embodiment, the control instruction of memory management circuitry 1043 is with firmware type
Formula carrys out implementation.Such as, memory management circuitry 1043 has microprocessor unit (not shown)
With read only memory (not shown), and above-mentioned control instruction is to be programmed in read only memory.
When memorizer memory devices 100 operates, above-mentioned control instruction can be performed by microprocessor unit
To complete the method responding host command of this exemplary embodiment.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 1043 is also
The specific region of fast storage wafer 106 can be stored in source code pattern (such as, quickly to deposit
Reservoir wafer 106 is exclusively used in the system area of storage system data) in.Additionally, memorizer management
Circuit 1043 have microprocessor unit (not shown), read only memory (not shown) and with
Machine access memorizer (not shown).Wherein, read only memory has driving code section, and when depositing
When memory controller 104 is enabled, microprocessor unit can first carry out this and drive code section to store
Control instruction in fast storage wafer 106 be loaded into memory management circuitry 1043 with
In machine access memorizer.Afterwards, microprocessor unit can operate above-mentioned control instruction to perform this model
The method responding host command of example embodiment.Additionally, in another exemplary embodiment of the present invention,
The control instruction of memory management circuitry 1043 a hardware pattern can also carry out implementation.
Buffer storage 1045 is coupled to memory management circuitry 1043, is configured to temporarily store and comes from master
The data of machine system 1000, or the temporary data coming from fast storage wafer 106.Specifically
It, is when host computer system 1000 storage device 100 to be write data into, corresponding write
The write data of instruction will first be kept in buffer storage 1045, then by memory management circuitry
Write data in buffer storage 1045 are write to fast storage wafer 106 by 1043.
Memory interface 1047 is coupled to memory management circuitry 1043, in order to make memorizer control
Device 104 couples with fast storage wafer 106 phase.Accordingly, Memory Controller 104 can be to soon
Speed memory chips 106 carries out relevant running.It is to say, be intended to write to fast storage wafer
The data of 106 can be converted to fast storage wafer 106 via memory interface 1047 and can accept
Form.
In another exemplary embodiment of the present invention, Memory Controller 104 also includes power management electricity
Road 3002.Electric power management circuit 3002 is coupled to memory management circuitry 1043, deposits in order to controlling
The power supply of reservoir storage device 100.
In the another exemplary embodiment of the present invention, Memory Controller 104 also include error checking with
Correcting circuit 3004.Error checking and correcting circuit 3004 are coupled to memory management circuitry 1043,
In order to perform error checking with correction program to guarantee the correctness of data.Specifically, storage is worked as
Device management circuit 1043 is when receiving the write instruction from host computer system 1000, error checking with
Correcting circuit 3004 can be that the data of this write instruction corresponding produce corresponding error checking and correction
Code (Error Checking and Correcting Code, ECC Code), and memorizer pipe
The data of this write instruction corresponding can be write with correcting code by reason circuit 1043 with corresponding error checking
Enter to fast storage wafer 106.Brilliant from fast storage when memory management circuitry 1043 afterwards
When sheet 106 reads data, error checking corresponding to these data and correcting code can be read simultaneously, and
Error checking can be according to this error checking and the correcting code data to being read with correcting circuit 3004
Perform error checking and correction program.
On average, memorizer memory devices 100 is per second can process about 10,000 host computer systems 1000
The instruction assigned.That is, execution time about 100 microsecond of each instruction.But store up at memorizer
Cryopreservation device 100 processed one instruct and will confirm that information-reply is to host computer system 1000 after, main frame
System 1000 just need to can assign new instruction through one period of waiting time (about 40 microsecond (μ s)).
It is not difficult to visualize, if memorizer memory devices 100 has often processed an instruction and all must expend about 40
Wait that host computer system 1000 assigns new instruction, memorizer memory devices 100 standby time of microsecond
Waiting that the time of new instruction will occupy the 40% of the execution time of an instruction, this situation can be to depositing
Reservoir storage device 100 performs the whole efficiency of instruction and adversely affects.
If but will confirm that in order to reduce standby time information-reply is to host computer system the most in advance
1000, then situation about exceeding the time limit new time for each instruction may be caused to produce.Specifically, such as Fig. 4 institute
Show, it is assumed that memorizer memory devices 100 is assigned write instruction CMD_1 by host computer system 1000, and
Time point t1Host computer system 1000 is by the write full data transmission corresponding to write instruction CMD-1 extremely
Buffer storage 1045.If memorizer memory devices 100 is at time point t1Just will confirm that information-reply
To host computer system 1000, host computer system 1000 is through waiting time TwAfter (about 40 microsecond) time
Between put t2Just can be by up to memorizer memory devices 100 under another instruction CMD_2.But, if
Write data are completely transmitted to buffer storage 1045, and memorizer memory devices 100 also needs to
Process time TpComplete write instruction CMD_1, represent that memorizer memory devices 100 can not be in the time
Point t2Start to process instruction CMD_2, and time point t must be waited until3Just can proceed by process.Writing
Entering to instruct CMD_1 can cause memorizer memory devices 100 trigger data to move the situation of execution of program
Under, owing to statistical data shows that to complete a data-moving program about needs the time of 0.5 second, this will
Make time point t2To time point t3Spacing long, and cause instruct CMD_2 overtime.
Base this, in order to improve memorizer memory devices 100 process instruction efficiency and avoid newly instructing
Overtime, the memory management circuitry in memorizer memory devices 100 described in this exemplary embodiment
1043 can be when receiving the instruction that host computer system 1000 is assigned, it is judged that this instruction is the need of longer
The execution time.If desired the execution time is shorter, then just will before instruction is really finished
Confirmation replies to host computer system 1000, allows host computer system 1000 can assign new instruction in advance.
But it is in order to obtain new instruction when preventing from carrying out relatively time consuming process, but new because not immediately treating
Instructing and cause overtime, memory management circuitry 1043 is judging that the instruction having been received by needs relatively
In the case of the long execution time, then just can respond after instruction is finished veritably.
In the middle of the various instructions that memorizer memory devices 100 is often assigned by host computer system 1000,
Must merged entity block or perform average abrasion and cause memorizer memory devices 100 trigger data
Move the write instruction of the execution of program, its execution time needed exceed well over general write, read,
Or the other kinds of instruction such as removing.Base this, below especially to receive from host computer system 1000
Write instruction as a example by come the present invention will be described.
In detail, when host computer system 1000 storage device 100 to be write data into,
Memory Controller 104 receives the write instruction from host computer system 1000 by adapter 102,
And kept in, by buffer storage 1045, the write data that host computer system 1000 is transmitted.And in main frame system
During system 1000 transmission write data, memory management circuitry 1043 can judge this time to receive
Write instruction is the need of the longer execution time.That is, whether trigger data holding of program can be moved
Row (data-moving produced by such as merged entity block or execution average abrasion).Real at this example
Executing in example, memory management circuitry 1043 is whether the number according to available physical blocks is less than one
Predetermined threshold level or specific parameter (such as perform produced parameter during average abrasion, or other make
Data produce the parameter moved) judge that write instruction whether trigger data moves the execution of program.
If write instruction not trigger data moves the execution of program, memory management circuitry 1043
Will be when writing data and being completely transmitted to buffer storage 1045, by correspondence write instruction really
Recognize information and be sent to host computer system 1000.But, if write instruction can trigger memorizer management electricity
Road 1043 performs the data-moving program of fast storage wafer 106, memory management circuitry 1043
Then can just will confirm that information is sent to host computer system 1000 when data-moving program finishes execution.
And host computer system 1000 is receiving after the confirmation of memorizer memory devices 100, just can
Again memorizer memory devices 100 is assigned another instruction.
Owing to host computer system 1000 is after the confirmation receiving memorizer memory devices 100, need
New instruction just can be assigned through one period of waiting time.It is to say, memorizer memory devices 100 exists
Processed one from after the instruction of host computer system 1000, minimum must through the above-mentioned waiting time
Can obtain and newly instruct and proceed by process.Therefore, memory management circuitry 1043 is true in instruction
Before being just disposed, (such as, the write data corresponding to write instruction are not yet written into and quickly deposit
Reservoir wafer 106) just notice host computer system 1000 prepares to assign new instruction ahead of time, and can promote and deposit
Reservoir storage device 100 performs the efficiency of the instruction that host computer system 1000 is assigned.
It addition, the write instruction assigned when host computer system 1000 can cause holding of data-moving program
When going and need the longer process time, in order to avoid obtaining the new instruction time to the new instruction of execution
Long, memory management circuitry 1043 can just respond main frame after data-moving program finishes execution
System 1000, to avoid causing new command operating time overtime because immediately treating new instruction
Situation.
In following exemplary embodiment, memory management circuitry 1043 is by setting judgement ginseng
Count and check the numerical value judging parameter in particular moment, determining to will confirm that information is sent to main frame
The opportunity of system 1000.
Specifically, write instruction is assigned by memory management circuitry 1043 in host computer system 1000
To memorizer memory devices 100, just judge one that parameter is set as the first particular value, and notify
Host computer system 1000 can start transmission write data.And be transferred to buffering in write data and deposit
The period of reservoir 1045, memory management circuitry 1043 judges write instruction, and whether trigger data is removed
The execution of shifting program.As long as and write full data transmission is deposited by host computer system 1000 to buffering
Reservoir 1045, host computer system 1000 can transmit an interrupt instruction to memorizer memory devices 100.
If memory management circuitry 1043 judges write instruction, not trigger data moves holding of program
OK, memory management circuitry 1043 can will determine that parameter is set as the second particular value.Now, if depositing
The interrupt instruction that reservoir storage device 100 receives from host computer system 1000 (represents write data
It is completely transferred to buffer storage 1045), memory management circuitry 1043 can go to check and judge ginseng
Number is the first particular value or the second particular value.Owing to judging that parameter has been set to the second particular value, because of
Even if this write instruction is disposed the most completely, memory management circuitry 1043 still can will confirm that letter
Breath is sent to host computer system 1000, in advance to inform that host computer system 1000 can prepare to assign the next one
Instruction.It follows that memory management circuitry 1043 may proceed to carry out the place of correspondence according to write instruction
Reason, that is, by the write data-moving in buffer storage 1045 to fast storage wafer 106.
Owing in this case, write instruction can't trigger memory management circuitry 1043 and perform data
Move program, so even and then memorizer memory devices 100 is assigned separately by host computer system 1000
One newly instructs, and new instruction also can be performed soon and overtime less easily occurs.
If but memory management circuitry 1043 judges that write instruction trigger data can move program
Performing, memory management circuitry 1043 judges the numerical value of parameter by not changing, and is ready for number
According to moving program.Period, if memorizer memory devices 100 receives host computer system 1000 and assigns
Interrupt instruction, memory management circuitry 1043 check judge that parameter is still the first particular value, table
Show the execution time that the most handled write instruction needs are longer, therefore memory management circuitry
1043 will not will confirm that information is sent to host computer system 1000, at this moment to avoid too fast receiving
Newly instruct but cannot immediately treat and produce the situation of overtime.Memory management circuitry 1043 meeting
Proceed data-moving program, and until data-moving program finishes execution, just will determine that ginseng
Number is set as the second particular value.Afterwards, if receiving the middle severed finger that host computer system 1000 transmits
Order, memory management circuitry 1043 will will confirm that information is sent to host computer system 1000.Further,
Memory management circuitry 1043 can be by the write data-moving in buffer storage 1045 to quickly depositing
Reservoir wafer 106 is to complete write instruction.
It is to say, the no matter memory management circuitry when host computer system 1000 sends interrupt instruction
By checking, the 1043 process actions carrying out what stage, all can judge that the numerical value of parameter is the
One particular value or the second particular value determine to transmit confirmation after a while or will confirm that letter immediately
Breath is sent to host computer system 1000.In comparison, can trigger because only comparing the write instruction of minority
The execution of data-moving program, the most at most of conditions can be because of first will confirm that information passes
Deliver to host computer system 1000 and make host computer system 1000 transmit next instruction in advance, and then reach
Reduce the purpose waiting the instruction issuing time.And when needing to carry out time-consuming data-moving program,
Also the situation of next instruction overtime it is avoided that.
Fig. 5 A, Fig. 5 B are according to the response host command depicted in the present invention one exemplary embodiment
The flow chart of method.
Referring to Fig. 5 A, the most as indicated in step 510, memorizer memory devices 100 receives main
The write instruction that machine system 1000 is assigned, now memory management circuitry 1043 is notified that main frame system
System 1000 can start to transmit corresponding write data.
The most in step 520, memory management circuitry 1043 will determine that parameter is set as first
Particular value.
As shown in step 530, memorizer memory devices 100 Receiving Host system 1000 is transmitted
Write data, these write data will be temporarily stored in buffer storage 1045.And as shown in step 540,
Memory management circuitry 1043 judges that write instruction whether trigger data moves the execution of program.Its
In, memory management circuitry 1043 can perform in the period of host computer system 1000 transmission write data
The judgement action of step 540.
If write instruction trigger data can't move the execution of program, as shown in step 550,
Memory management circuitry 1043 will determine that parameter is set as the second particular value.
If but write instruction trigger data can move the execution of program, the most as shown in step 560,
Memory management circuitry 1043 starts to perform data-moving program.When data-moving program has performed
Bi Shi, as shown in step 570, memory management circuitry 1043 will determine that parameter is set as second
Particular value.
Last as shown in step 580, memory management circuitry 1043 will be temporarily stored into buffer storage
Write data in 1045 store to fast storage wafer 106, to complete write instruction.
Therefore in the period of each step shown in Fig. 5 A, once host computer system 1000 will write number
According to being completely transferred to buffer storage 1045, host computer system 1000 can up to will be deposited under interrupt instruction
Reservoir storage device 100.Base this, when receiving the interrupt instruction that host computer system 1000 transmits,
Shown in step 5001 as shown in Figure 5 B, memory management circuitry 1043 checks and judges that parameter is
No is the second particular value.If it is not, then as shown in step 5003, memory management circuitry 1043 is temporary
Not will confirm that information is sent to host computer system 1000.If so, memory management circuitry 1043 will be really
Recognize information and be sent to host computer system 1000.
As shown in Fig. 5 A, Fig. 5 B, before judging that parameter is set to the second particular value, storage
Device management circuit 1043 is sent to host computer system 1000 all without the information of will confirm that.And judging ginseng
After number is set to the second particular value, as long as receiving during host computer system 1000 transmits
Severed finger makes, and no matter whether write instruction is finished, and memory management circuitry 1043 all can be by really
Recognize information and be sent to host computer system 1000.
In sum, the method for response host command of the present invention, Memory Controller and
According to write instruction whether memorizer memory devices is when receiving from the write instruction of host computer system,
Memorizer memory devices trigger data is caused to move the execution of program, to determine at different time points
The confirmation of write instruction is sent to host computer system.Consequently, it is possible to for will not trigger data
Move the write instruction of program, transmit the time of confirmation ahead of time, and then host computer system can be carried
Front by up to memorizer memory devices under next instruction, process and refer to improving memorizer memory devices
The whole efficiency of order.Additionally for the write instruction of data-moving program can be caused, then wait pending data
Host computer system is just responded, to prevent the next instruction received from producing after moving program finishes execution
The situation of overtime.
Although the present invention discloses as above with embodiment, so it is not limited to the present invention, any
Those of ordinary skill in art, when making a little change and retouching, without deviating from this
The spirit and scope of invention.
Claims (21)
1. the method responding host command, is used for having a fast storage wafer and and delays
Rushing a memorizer memory devices of memorizer, the method includes:
Receive the write instruction that a host computer system is assigned；
Judge whether this write instruction causes this memorizer memory devices to trigger a data-moving program
Execution；And
Deposit if it is not, be then completely transmitted to this buffering in the write data corresponding to this write instruction
During reservoir, by a confirmation of write instruction being sent to this host computer system.
The method of response host command the most according to claim 1, wherein this data-moving
Program includes the physical blocks merging this fast storage wafer and the data-moving produced, or to this
The data-moving that fast storage wafer performs average abrasion and produces.
The method of response host command the most according to claim 1, is wherein judging that this is write
Enter whether instruction causes this memorizer memory devices to trigger the step of execution of this data-moving program
Afterwards, the method also includes:
The most then when this data-moving program finishes execution, this confirmation is sent to this master
Machine system.
The method of response host command the most according to claim 1, is wherein receiving this master
After the step of this write instruction that machine system is assigned, the method also includes:
Judge that by one parameter is set as one first particular value.
The method of response host command the most according to claim 4, the most also includes:
If it is determined that this write instruction does not cause the execution of this data-moving program, then in this write instruction
These corresponding write data are completely transmitted to this buffer storage, this judgement parameter are set
It it is one second particular value；And
If it is determined that this write instruction causes the execution of this data-moving program, then in this data-moving journey
When sequence is finished, this judgement parameter is set as this second particular value.
The method of response host command the most according to claim 5, the most also includes:
Receive this host computer system assign an interrupt instruction time, check this judgement parameter be this first
Particular value or this second particular value；
If this judgement parameter is this first particular value, the most do not transmit this confirmation to this main frame system
System；And
If this judgement parameter is this second particular value, then transmit this confirmation to this host computer system.
The method of response host command the most according to claim 6, wherein this interrupt instruction
It is to assign when this host computer system judges by this write full data transmission to this buffer storage
To this memorizer memory devices.
8. a Memory Controller, including:
One host system interface, in order to couple a host computer system；
One memory interface, in order to couple a fast storage wafer；
One buffer storage；And
One memory management circuitry, be coupled to this host system interface, this memory interface with this delay
Rushing memorizer, the write that wherein this memory management circuitry is assigned in order to receive this host computer system refers to
Order, and judge whether this write instruction triggers the execution of a data-moving program,
If it is not, this memory management circuitry is also in order in the write data corresponding to this write instruction
When being completely transmitted to this buffer storage, by should a confirmation of write instruction be sent to
This host computer system.
Memory Controller the most according to claim 8, wherein this data-moving program bag
Include the data-moving merging the physical blocks of this fast storage wafer and produce, or this is quickly deposited
The data-moving that reservoir wafer performs average abrasion and produces.
Memory Controller the most according to claim 8, if wherein this memorizer management
This write instruction of circuit judges triggers the execution of this data-moving program, and this memory management circuitry is also
In order to when this data-moving program finishes execution, this confirmation is sent to this host computer system.
11. Memory Controllers according to claim 8, wherein this memorizer management electricity
By one, road is also in order to, after receiving this write instruction that this host computer system is assigned, to judge that parameter sets
It it is one first particular value.
12. Memory Controllers according to claim 11, wherein this memorizer management electricity
Road is also in order to when judging the execution that this write instruction will not trigger this data-moving program, to write at this
Enter these write data corresponding to instruction to be completely transmitted to this buffer storage, this judgement is joined
Number is set as one second particular value, and is judging that this write instruction can trigger this data-moving program
Execution time, when this data-moving program finishes execution, this judgement parameter being set as, this is second special
Definite value.
13. Memory Controllers according to claim 12, wherein this memorizer management electricity
Road also in order to when receiving the interrupt instruction that this host computer system is assigned, checks that this judges that parameter is as being somebody's turn to do
First particular value or this second particular value,
If this judgement parameter is this first particular value, this memory management circuitry does not transmit this confirmation letter
Cease to this host computer system,
If this judgement parameter is this second particular value, this memory management circuitry transmits this confirmation
To this host computer system.
14. Memory Controllers according to claim 13, wherein this interrupt instruction is to work as
This host computer system judges this write full data transmission to this buffer storage the most up to should
Memory management circuitry.
15. 1 kinds of memorizer memory devices, including:
A connector, in order to couple a host computer system；
One fast storage wafer；And
One Memory Controller, is coupled to this fast storage wafer and this adapter, and wherein this is deposited
Memory controller includes a buffer storage,
This Memory Controller is in order to receive the write instruction that this host computer system is assigned, and judges to be somebody's turn to do
Whether write instruction triggers the execution of a data-moving program,
If it is not, this Memory Controller is also in order at the write data quilt corresponding to this write instruction
When being completely transferred to this buffer storage, by a confirmation of write instruction being sent to this
Host computer system.
16. memorizer memory devices according to claim 15, wherein this data-moving journey
Sequence includes the physical blocks merging this fast storage wafer and the data-moving produced, or fast to this
The data-moving that speed memory chips performs average abrasion and produces.
17. memorizer memory devices according to claim 15, if wherein this memorizer control
Device processed judges that this write instruction can trigger the execution of this data-moving program, and this Memory Controller is also
In order to when this data-moving program finishes execution, this confirmation is sent to this host computer system.
18. memorizer memory devices according to claim 15, wherein this memorizer controls
By one, device is also in order to, after receiving this write instruction that this host computer system is assigned, to judge that parameter sets
It it is one first particular value.
19. memorizer memory devices according to claim 18, wherein this memorizer controls
Device is also in order to when judging the execution that this write instruction will not trigger this data-moving program, to write at this
Enter these write data corresponding to instruction to be completely transmitted to this buffer storage, this judgement is joined
Number is set as one second particular value, and is judging that this write instruction can trigger this data-moving program
Execution time, when this data-moving program finishes execution, this judgement parameter being set as, this is second special
Definite value.
20. memorizer memory devices according to claim 19, wherein this memorizer controls
Device also in order to when receiving the interrupt instruction that this host computer system is assigned, checks that this judges that parameter is as being somebody's turn to do
First particular value or this second particular value,
If this judgement parameter is this first particular value, this Memory Controller does not transmit this confirmation
To this host computer system,
If this judgement parameter is this second particular value, this Memory Controller transmits this confirmation extremely
This host computer system.
21. memorizer memory devices according to claim 20, wherein this interrupt instruction is
When this host computer system judges by this write full data transmission to this buffer storage the most up to
This Memory Controller.
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| US20180373653A1 (en) * | 2017-06-21 | 2018-12-27 | Hewlett Packard Enterprise Development Lp | Commitment of acknowledged data in response to request to commit |
| CN108595360A (en) * | 2018-04-28 | 2018-09-28 | 北京东远润兴科技有限公司 | A kind of memory recorder based on M.2 interface and PowerPC |
| CN111143898B (en) * | 2018-11-05 | 2022-06-14 | 瑞昱半导体股份有限公司 | Data protection method for pluggable memory device |
| TWI755739B (en) * | 2020-05-26 | 2022-02-21 | 慧榮科技股份有限公司 | Memory controller and data processing method |
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| CN1372202A (en) * | 2001-02-21 | 2002-10-02 | 富士通株式会社 | Semiconductor storage device and information process unit |
| US7222211B2 (en) * | 2005-03-14 | 2007-05-22 | Phison Electronics Corporation | Virtual USB flash memory storage device with PCI express interface |
| CN101866320A (en) * | 2009-04-14 | 2010-10-20 | 群联电子股份有限公司 | Data management method and flash memory storage system and controller using the same |
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| CN101571832B (en) * | 2008-04-29 | 2013-07-17 | 群联电子股份有限公司 | Data writing method, quick flashing memory system using same and a controller thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1372202A (en) * | 2001-02-21 | 2002-10-02 | 富士通株式会社 | Semiconductor storage device and information process unit |
| US7222211B2 (en) * | 2005-03-14 | 2007-05-22 | Phison Electronics Corporation | Virtual USB flash memory storage device with PCI express interface |
| CN101866320A (en) * | 2009-04-14 | 2010-10-20 | 群联电子股份有限公司 | Data management method and flash memory storage system and controller using the same |
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