JP2000148580A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of evading a trouble of burdening access control with a control command string even when operation frequency is further increased and continuously executing reading and writing operation from/in a plurality of banks without interrupting it. SOLUTION: The semiconductor storage device having plural banks A, B each of which consists of a plurality of memory cells arrayed like a matrix and a data I/O line extended in the column direction and capable of successively accessing data in a specified row address is provided with a bank judging circuit 13 for judging a 1st bank to be accessed at first out of both the banks A, B, a row address counter circuit 14 for counting row addresses to be continuously accessed in the 1st bank and a bank switching circuit 15 for accessing the 2nd bank continuously after the end of access to the highest column in the 1st band and constituted so as to continuously execute reading or writing operation by alternately switching the 1st and 2nd banks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which inputs and outputs data in synchronization with an input clock.

[0002]

2. Description of the Related Art In recent years, with an increase in processing speed in an image processing apparatus, there has been a demand for a memory capable of reading and writing image information at high speed. As one of the memories meeting this demand, a synchronous DRAM or a high-speed DRAM called a synchronous graphic RAM is becoming widespread.

For example, a synchronous DRAM has two banks provided with independent address spaces, and each bank can operate independently. The synchronous DRAM realizes high-speed access to data by performing a burst operation of sequentially accessing data stored at consecutive addresses in the same row (row) space.

[0004]

At the time of controlling a synchronous memory such as the above-mentioned conventional synchronous DRAM or the like, a read or write operation is performed by combining a plurality of control commands from a CPU or the like. Need to repeatedly input the corresponding command sequence. Therefore, in order to increase the efficiency of data processing by performing processing such as burst operation, that is, bank interleaving,
Complicated processing must be required of the memory controller. The control command is an operation command for the memory, and causes a precharge of an activated row address, an access to an address specified by an address signal in a certain bank, and the like.

In the synchronous DRAM, the operating frequency exceeds 100 MHz, the speed is further increased to 125 MHz or 143 MHz, and the control command sequence tends to be more complicated, which is a big problem for the memory controller. It is a burden.

In view of the above, the present invention can avoid a problem that a control command string burdens access control even when the operating frequency is further increased, and can continuously perform read and write operations on a plurality of banks. It is another object of the present invention to provide a semiconductor memory device which can be executed without interruption.

[0007]

In order to achieve the above object, a semiconductor memory device according to the present invention has a plurality of banks composed of a plurality of memory cells arranged in a matrix, and each bank is arranged in a column direction. A semiconductor memory device having an extended data input / output line and sequentially accessing within a designated row address; a bank determining means for determining a first bank to be accessed first among the plurality of banks; First
A row address counter for counting a row address continuously accessed in the first bank, and bank switching means for successively accessing the second bank after the access to the uppermost column in the first bank is completed. And wherein the access is alternately switched between the first bank and the second bank to continuously perform a read or write operation.

In the semiconductor memory device according to the present invention, in a circuit portion operating in synchronization with an externally supplied clock, a row address counter continuously increments and counts a row address of each bank, and a bank switching means. Follows the counted row address in the first bank followed by the second
To the counted row address in the bank. Unlike a conventional semiconductor memory device that operates according to a complicated control command from a CPU or the like, such a semiconductor memory device of the present invention receives a specific control command from a CPU or the like and performs a read or write operation between a plurality of banks. Can be automatically and continuously performed. Therefore, in the present semiconductor memory device, even when the operating frequency is further increased, it is possible to avoid a problem that the control command sequence becomes a burden during access control. Further, regardless of the column (column) length in one row address, continuous read or write operation can be performed for the entire memory cell, so that a large amount of data can be continuously read or written. Control commands can be made more efficient.

Here, the first bank indicates a bank on a lower side with respect to a bank address, the second bank indicates a bank on an upper side with respect to a bank address, and the bank switching means may switch from a lower bank to an upper bank. It is preferable to activate the data input / output line at the same row address when transferring access to a bank, and activate the data input / output line at a subsequent row address when transferring from an upper bank to a lower bank. In this case, it is possible to prevent a problem of accessing the same address to which data has already been written next, and realize a smooth read or write operation.

Alternatively, instead of the above, the first bank indicates a lower bank with respect to a bank address, the second bank indicates a higher bank with respect to a bank address, and the bank switching means comprises: It is preferable to activate the data input / output line at the same row address when shifting access from the upper bank to the lower bank, and to activate the data input / output line at the succeeding row address when shifting from the lower bank to the upper bank. . In this case, it is possible to prevent a problem that the same address where data has already been written is accessed next, and realize a smooth read or write operation.

A semiconductor memory device according to the present invention has a plurality of banks composed of a plurality of memory cells arranged in a matrix.
Each bank has a data input / output line extending in the column direction,
In a semiconductor memory device of a type in which access is sequentially performed within a designated row address, a first bank to be accessed first among the plurality of banks is determined, and a row to be continuously accessed in the first bank is determined. Counting an address, and after completing the access of the uppermost column in the first bank, switch the bank for subsequent access in the second bank, and switch between the first bank and the second bank. And the read or write operation is continuously performed by alternately switching the access.

In the semiconductor memory device according to the present invention, even when the operating frequency is further increased, it is possible to avoid a problem that a command string burdens access control, and to continuously perform read and write operations on a plurality of banks without interruption. Can be performed.

[0013]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a semiconductor memory device such as a synchronous DRAM according to a first embodiment of the present invention.

The semiconductor memory device according to this embodiment is
It has cell arrays 29A and 29B provided in a main storage device (memory). The cell arrays 29A and 29B are:
Each of the banks A and B includes a plurality of memory cells (not shown) arranged in a matrix. Each of the banks A and B has a row decoder 31 for selecting an address (row address) in the row direction, a column decoder 30 for selecting an address (column address) in the column direction, and a selected bank. And a sense amplifier 32 for reading stored contents in the memory cells.

In this embodiment, banks A and B
Have the same addresses in the matrix direction, bank A forms the lower bank with respect to the bank address, and bank B forms the upper bank with respect to the bank address. Each of the banks A and B has a data input / output line extending in the column direction, and the semiconductor memory device has a format of sequentially accessing a designated row address.

The semiconductor memory device further includes a clock generator 21, a mode register 22, a command decoder 23, a control logic circuit 24, a row address
Buffer 25, refresh counter 26, column
An address buffer 27, a burst counter 28, a bank determination circuit 13, a row address counter 14, and a bank switching circuit 15 are provided.

The clock generator 21 receives the clock signal CLK and the clock enable signal CKE, and supplies the clock signal to the command decoder 23, the bank switching circuit 15, and the latch circuit 11, respectively.

The mode register 22 supplies a signal corresponding to a mode to be executed to the control logic circuit 24 when an address signal Add is sent from a CPU (not shown).

The command decoder 23 has an address signal
Add, the output of the clock generator 21, and each low active chip select signal / CS, / RAS signal
(RowAccess Strobe), / CAS signal (Column Access Str
obe) and the write enable signal / WE are input respectively,
The output is supplied to the control logic circuit 24. / R
The AS signal is a signal for notifying that a row (row) address is to be passed, the / CAS signal is a signal for notifying that a column (column) address is to be passed,
Write enable signal / WE is a signal for permitting writing.

The control logic circuit 24 includes a command
When each output of the decoder 23, the clock generator 21 and the mode register 22 is input, a control signal is generated to generate a row address buffer 25, a sense amplifier 32, a column address buffer 27, a data control circuit. 10 and the latch circuit 11 respectively.

The row address buffer 25 stores a row address in the input bank address signal Add, and the column address buffer 27 stores a column address in the input address signal Add. . The refresh counter 26 counts refresh addresses. The burst counter 28 counts the burst length of read data and write data. The burst length indicates the maximum data length at the column address.

The bank determination circuit 13 determines a bank to be accessed first among the banks A and B. For example,
When the burst length is set as (full page) for all column addresses in a specific row address in the bank, the bank address signal Add is supplied to the bank determination circuit 13 when a row address in the bank is selected. Since the bank is supplied, the bank determination circuit 13 can determine which bank has been selected.

The row address counter 14 counts while incrementing a row address continuously accessed in the bank A (or B) determined by the bank determination circuit 13.

The bank switching circuit 15 outputs the bank A counted by the row address counter circuit 14.
At the end of access to the top row in (or B) (after the end)
The bank A (or A) is shifted to the data input / output line at the row address to be subsequently accessed, and the row address of the bank A (or B) that has been accessed is precharged, so that the bank A and the bank B has a function as a bank switching means for alternately switching the access between them and performing a read or write operation continuously.

For example, when incrementing the column address of the highest address of the selected bank A (or B), the column address is supplied to the bank switching circuit 15. The bank switching circuit 15 shifts the row address activated in the unselected bank B (or A) to, for example, the column address at address 0. Further, the bank switching circuit 15 internally issues a precharge command to the data input / output line at the row address of the selected bank when switching to the next bank, and automatically performs precharge. Further, after the end of the precharge, the row address counter 14 increments the row address of the selected bank and activates the incremented row address.

The semiconductor memory device further includes a data control circuit 10, a latch circuit 11, and an input / output buffer 1.
2

The data control circuit 10 receives a signal from the control logic circuit 24 and controls the column decoder 30 and the latch circuit 11, respectively. The latch circuit 11 receives the clock signal from the clock generator 21, the signal from the data control circuit 10, and the signal from the control logic circuit 24, latches necessary signals with the clock signal, and takes in the signals.
Send to input / output buffer 12. The DQM in FIG.
This signal masks input / output data. DQ indicates a data input / output pin, which means data-in for write data and data-out for read data.

The operation of this embodiment will be described below. First, the burst length in the semiconductor memory device is full
The read operation started from the bank A when the page is set will be described with reference to FIG. 1 and the timing chart of FIG.

FIG. 2 is a timing chart in the bank A when the last address of the column address is 255. In FIG. 2, the horizontal direction indicates the time axis based on the clock signal from the clock generator 21, and the vertical direction indicates the signal line axis. FIGS. 7A to 7D respectively show states of a clock signal, a control command, a bank address signal Add, and an input / output pin DQ.

In FIG. 2A, the clock signals are T0 to Tb.
ＴTb + 4... At a predetermined cycle. FIG.
In the control command of (b), ACT indicates an active command, and READ indicates a read command. Fig. 2 (c)
"RAa" indicates the row address a of the bank A, and "CAb" indicates the column address b of the bank A.

In the input / output pin DQ of FIG.
“Aab” is output data at row address a and column address b of bank A, “QAab + 1” is output data at row address a and column address b + 1 of bank A, and “QBa0” is row address a of bank B.
The output data at column address 0 is shown at the address.

First, at time T1, when an active command (ACT) and a row address a of the bank A are input as a control command, the active command (ACT) is input to the command decoder 23, and the row address a is input to the command decoder 23. Each is supplied to a row address buffer 25. Thus, the data input / output line at the row address of the bank A selected by the address signal Add is activated.

Further, since the address signal Add is supplied to the bank determination circuit 13 via the row address buffer 25, the bank determination circuit 13 determines which bank has been selected based on the address signal Add. Therefore, the bank switching circuit 15 activates the data input / output line at the same row address a as that of the bank A in the unselected and higher bank B by the output.

Next, at time T3, a read command (READ)
And the column address b of the bank A, the read command (READ) is supplied to the command decoder 23, the column address is supplied to the column address buffer 27, and each rising edge of the clock signal after time T5 Data is output in synchronization with.

The output data is data obtained by incrementing the column address by the burst counter 28 with the data at the row address a and the column address b in the bank A as the head. When the column address of the highest address in bank A is incremented, this column address is supplied to bank switching circuit 15, so that column address 0 in row address a activated in bank B (data input / output) Line).

Further, the bank switching circuit 15 automatically issues a precharge command internally to the data input / output line at the row address in the bank A in which the read operation has been completed, and automatically precharges the data. address·
The row address is incremented by the counter 14,
The data input / output line at this row address is activated.

Similarly, in the bank B, when the column address at the highest address is incremented, the column address is supplied to the bank switching circuit 15, so that the column address at the address a + 1 of the row address activated in the bank A is incremented. 0
Shift to address (data input / output line).

Next, a precharge command is internally issued for the row address in the bank B where the read operation has been completed to automatically perform precharge, and the row address is incremented by the row address counter 14. Activate the data input / output line at the row address. As a result, the reading operation is continuously performed between the banks A and B without interruption.

On the other hand, a read operation started from bank B when the burst length in the semiconductor memory device is set to a full page will be described with reference to FIG. 1 and a timing chart of FIG.

FIG. 3 shows that the highest address of the column address is 255
6 is a timing chart in the bank B in the case of FIG.
In FIG. 3, the horizontal direction indicates the time axis based on the clock signal from the clock generator 21, and the vertical direction indicates the signal line axis. FIGS. 6A to 6D show a clock signal,
Control command, address signal Add, and input / output pin DQ
The state in is shown.

In FIG. 3A, the clock signals are T0 to Tb.
ＴTb + 4... At a predetermined cycle. FIG.
In the control command of (b), ACT indicates an active command, and READ indicates a read command. Fig. 3 (c)
"RBa" indicates the row address a of the bank B, and "CBb" indicates the column address b of the bank B.

In the input / output pin DQ of FIG.
Bab ”is the row address a of bank B and the column address b
The output data at the address, "QBab + 1" is bank B
Output data at a row address a and a column address b + 1, and "QAa + 1" is a row address a +
Output data at column address 0 is shown at address 1.

First, at time T1, when an active command (ACT) and a row address a of the bank B are input as control commands, the active command (ACT) is input to the command decoder 23, and the row address a is input to the command decoder 23. Each is input to the row address buffer 25. As a result, the data input / output line at the row address of the bank B selected by the address signal Add is activated.

Further, since the address signal Add is supplied to the bank determination circuit 13 via the row address buffer 25, the bank determination circuit 13 determines which bank has been selected based on the address signal Add. , The bank switching circuit 15 outputs the row address a +
Activate the data input / output line at address 1.

Next, at time T3, a read command (READ)
And the column address b of the bank B, the read command (READ) is supplied to the command decoder 23, the column address is supplied to the column address buffer 27, and each rising edge of the clock signal after time T5 Data is output in synchronization with.

The output data is data obtained by incrementing the column address by the burst counter 28 starting from the data at the row address a and the column address b in the bank B. When the column address of the highest address in the bank B is incremented, this column address is supplied to the bank switching circuit 15, so that the row address a + 1 precharged in the bank A
Shift to column address 0 at the address.

Further, the bank switching circuit 15 internally issues a precharge command to a row address in the bank B where the read operation has been completed, and automatically performs precharge. Next, the row address counter 14 increments the row address, and the bank switching circuit 15
Activates the data input / output line at this row address.

Similarly, in the bank A, when the column address of the highest address is incremented, the column address is supplied to the bank switching circuit 15, so that the column address in the row address a + 1 precharged in the bank B is provided. Shift to address 0.

Next, the bank switching circuit 15 internally issues a precharge command to the row address in the bank A where the read operation has been completed, and automatically performs precharge. Next, the row address counter 14
Increments the row address, and the bank switching circuit 1
5 activates the row address. Thus, the read operation is continuously and continuously performed between the banks B and A.

As described above, in this embodiment, when the reading or writing operation is continuously performed between the banks A and B without interruption, the same operation is performed when shifting from the lower bank A to the upper bank B. When shifting from the upper bank B to the lower bank A, the row address is shifted to the following row address.

In this embodiment, when the burst length which is a set of continuous signals or data handled as one unit according to a specific rule is set to a full page, it is determined which bank the first access points to. Bank determination circuit 13, a row address counter 14 for incrementing a row address, and a bank for executing interleaving in which continuous read and write data are allocated between banks and adjacent addresses are allocated to different banks. And a switching circuit 15. Thus, for example, when the burst length is set to the full page, the read and write operations for the bank A and the bank B can be alternately performed without interruption, and control commands can be made more efficient.

Next, a second embodiment of the present invention will be described. In the first embodiment, when performing a continuous read or write operation between the banks A and B without interruption, when shifting from the lower bank A to the upper bank B, the data input / output line at the same row address is When shifting from the upper bank B to the lower bank A, the data is shifted to the data input / output line at the subsequent row address.
However, in the present embodiment, the data input / output lines at the same row address are used when shifting from the upper bank B to the lower bank A, and the data input / output lines at the subsequent row addresses are used when shifting from the lower bank A to the upper bank B. It has a configuration for shifting to data input / output lines.

In this embodiment, in order to realize the above configuration, when a row address of a bank is selected, when the bank B is selected, the bank judgment circuit 13 causes the data at the same row address in the unselected bank A to be selected. Activate the input / output lines simultaneously. When the bank A is selected, the same row address in the unselected bank B is incremented by the row address counter 14, and the data input / output lines at the row address are simultaneously activated. According to the second embodiment having such a configuration, the same effect as that of the first embodiment can be obtained.

The burst length in the first and second embodiments can be changed to an arbitrary value (2, 4, 8). When the burst length is an arbitrary value other than the full page, a plurality of banks can be alternately read at an arbitrary data length and read and written without interruption.

In the first and second embodiments, the CP
Unlike a conventional semiconductor memory device that operates according to a complicated control command from the U or the like, when a specific control command is received from a CPU or the like, a read or write operation is automatically and continuously performed between the banks A and B. be able to. Therefore, in the present semiconductor memory device, even when the operating frequency is further increased, it is possible to avoid a problem that the control command sequence becomes a burden during access control. Further, regardless of the column (column) length in one row address, continuous read or write operation can be performed for the entire memory cell, so that a large amount of data can be continuously read or written. Control commands can be made more efficient.

In the first and second embodiments, the example in which the bank has two banks A and B has been described. However, the present invention is not limited to this, and the present invention may be applied to a semiconductor having three or more banks. The present invention can also be applied to a storage device. In this case, the same effects as those of the first and second embodiments can be obtained.

Although the present invention has been described based on the preferred embodiment, the semiconductor memory device of the present invention is not limited to the configuration of the above-described embodiment, but rather the configuration of the above-described embodiment. Various modifications and changes of the present invention are also included in the scope of the present invention.

[0058]

As described above, according to the semiconductor memory device of the present invention, even if the operating frequency is further increased, it is possible to avoid the problem that the control command sequence becomes a burden during access control. Read and write operations to the banks can be executed continuously without interruption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a bank A when the last address of a column address is 255.

FIG. 3 is a timing chart in a bank B when the last address of a column address is 255.

[Explanation of symbols]

 10: Data control circuit 11: Latch circuit 12: I / O buffer 13: Bank determination circuit 14: Row address counter 15: Bank switching circuit 21: Clock generator 22: Mode register 23: Command decoder 24: Control Logic circuit 25: Row address buffer 26: Refresh counter 27: Column address buffer 28: Burst counter 29A, 29B: Cell array (bank A, bank B) 30: Column decoder 31: Row decoder 32: sense amplifier

Claims (4)

[Claims] 1. A format having a plurality of banks composed of a plurality of memory cells arranged in a matrix, each bank having a data input / output line extending in a column direction, and sequentially accessing a designated row address. In the semiconductor memory device, bank determination means for determining a first bank to be accessed first among the plurality of banks, and a row address counter for counting a row address continuously accessed in the first bank And bank switching means for successively accessing the second bank after the end of the access to the uppermost column in the first bank, wherein the bank switching means alternately switches between the first bank and the second bank. A semiconductor memory device wherein a read or write operation is continuously performed by switching access. 2. The bank according to claim 1, wherein the first bank indicates a bank on a lower side with respect to a bank address, the second bank indicates a bank on an upper side with respect to a bank address, and the bank switching means includes a bank from a lower bank to an upper bank. 2. The data input / output line at the same row address is activated when the access is shifted to, and the data input / output line at the subsequent row address is activated when shifting from the upper bank to the lower bank. 3. The semiconductor memory device according to claim 1. 3. The bank according to claim 1, wherein the first bank indicates a lower bank with respect to a bank address, the second bank indicates a higher bank with respect to a bank address, and the bank switching means comprises: 2. The data input / output line at the same row address is activated when the access is shifted to, and the data input / output line at the subsequent row address is activated when shifting from the lower bank to the upper bank. 3. The semiconductor memory device according to claim 1. 4. A format having a plurality of banks composed of a plurality of memory cells arranged in a matrix, each bank having a data input / output line extending in a column direction, and sequentially accessing a designated row address. In the semiconductor memory device, a first bank to be accessed first among the plurality of banks is determined, and a row address continuously accessed in the first bank is counted. After the access of the uppermost column of the first bank is completed, the bank is switched for subsequent access in the second bank, and the access is alternately switched between the first bank and the second bank to perform a read or write operation. Is continuously performed.