JPH09134589A - Semiconductor memory device and operating method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a data bus width with a degree of complexity near to that of a general-purpose DRAM, by selecting a bank to be selected from two banks in accordance with a control signal including a column-series control signal and, sorting banks by a column series, not by a row series. SOLUTION: A pair of global data lines (RWD, BRWD) are arranged at opposite sides of a row decoder (R/D) 3 for selecting of rows in a memory cell array 1 via the memory cell array 1. Pairs of local data lines (DQ, BDQ) of areas 5-1 and 5-2 including a group of sense amplifiers S/A are connected to the RWD, BRWD via DQ buffers (DBQ) 7. Either of banks 1 and 2 sorted in terms of a row, not a column is selected by controlling each DQB by means of a bank control circuit (BD) 9. In this manner, while a consuming power, a chip size, and a degree of complexity subsequent to the arrangement of the circuit 9 are maintained close to those of a general-purpose DRAM, a data bus width is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having banks.

[0002]

2. Description of the Related Art A dynamic type R used as a main memory or a random access port of an image memory
In recent years, AM (hereinafter abbreviated as DRAM) is required to have a function of inputting / outputting a large amount of data at a higher speed. As a function to increase the so-called data bus width, in addition to the conventional first page mode, recently, extended data out (Extended Data Out:
The EDO mode has come into use.

FIG. 9 is a waveform diagram of main signals in a general-purpose DRAM. In FIG. 9, an output waveform Dout (FP) when using the first page mode (hereinafter, abbreviated as FP mode or FP) and an extended data out mode (hereinafter, abbreviated as EDO mode or EDO) were used. And the output waveform Dout (EDO) at that time are shown.

As shown in FIG. 9, the common feature between the FP mode and the EDO mode is that the column address strobe signal (/
Each time (CAS) drops, the column address is fetched and the data corresponding to the fetched column address is output.

On the other hand, the difference between the FP mode and the EDO mode is the relationship between the transition of the / CAS signal and the output. FP
In the mode, the output changes to the high output impedance state as the / CAS signal rises, and / CAS of the next cycle
When the signal drops, this operation is repeated to output the data corresponding to the next column address.

On the other hand, in the EDO mode, / C
Even if the AS signal rises, the output does not become a high output impedance state, the output is maintained, and when the / CAS signal falls in the next cycle, the data corresponding to the next column address is switched at once.

Comparing the two, if the length of one / CAS signal cycle is equal, the EDO mode has a longer data output time. Therefore, in order to secure the same output time, the length of the / CAS signal cycle is shorter in the EDO mode. That is, the EDO mode has a larger data bus width per unit time than the FP mode.

The above operation will now be described in connection with the configuration of a DRAM core (in this specification, the core indicates a portion in which a memory cell array, a sense amplifier, a column gate, a data line, etc. are integrated).

FIG. 10 is a diagram showing a core of a general-purpose DRAM. FIG. 10A is a block diagram and FIG. 10B is a circuit diagram.
As shown in FIGS. 10A and 10B, memory cells are arranged at the intersections of the word lines WL and the bit lines BL of the memory cell array. Recent DRAM (especially 16M D
In the RAM and later), the reduction of the sense amplifier (S / A) cannot keep up with the reduction of the memory cell, and the principle of the 1-column 1-sense amplifier of the folded bit line system has been broken up to that point. That is, since the arrangement pitch of the sense amplifiers (S / A) cannot be matched with the arrangement pitch of the memory cells, the bit line pairs (BL, BBL) are drawn out every other column to the left and right of the memory cell array to arrange the sense amplifiers. doing. With such a device, the sense amplifier (S
The arrangement pitch of / A) is twice the arrangement pitch of the memory cells. The bit line pair (BL, BBL) is a sense amplifier (S / S) provided on the left and right of the memory cell array.
A) and the column gate (C / G) are connected to the local data line pair (DQ, BDQ). The local data line pair (DQ, BDQ) is connected to the global data line pair (RWD, BRWD) via the DQ buffer (DQB), and is connected to a peripheral circuit portion including an input / output circuit (not shown).

Here, the column address (CAj; j =
Decoding regarding 0, 1, ..., M; m is a positive integer) will be described. A column decoder (not shown) decodes a part of the column address and selects only the column selection line (CSL) corresponding to the decoded address.
Among the column gates (C / G), the one connected to the selected column select line (CSL) becomes conductive. In general, a plurality of bit line pairs (BL, BBL) are selected by one column select line (CSL), and the same number of local data line pairs (DQ, BDQ) as the selected bit line pairs (BL, BBL) are selected. The data is read out respectively. The DQ buffers (DQB) provided on the left and right of the memory cell array perform decoding on the remaining column addresses. Regarding the DQ buffer (DQB), only one of the plurality is selected. In every case of FP mode and EDO mode, every / CAS signal cycle,
The above decoding is repeated.

By the way, in order to further increase the data bus width per unit time, recently, a synchronous DRA has been used.
M has appeared. One of the features of synchronous DRAM is
Serial clock signal SCL with a cycle time shorter than the / CAS signal cycle of conventional general-purpose DRAM
K is given from the outside, and data is input / output in synchronization with this SCLK signal. As a result, the synchronous DRAM is better than the EDO mode of general-purpose DRAM.
The data bus width per unit time can be further increased.

Another characteristic of the synchronous DRAM is that it has a row-system plural bank configuration. FIG.
It is a block diagram of a synchronous DRAM having a two-bank configuration.

The block shown in FIG. 11 corresponds to the block of the general-purpose DRAM shown in FIG. The circuit configuration of the memory cell array of the synchronous DRAM is similar to that of the general-purpose DRAM shown in FIG.

Synchronous DR compared to general-purpose DRAM
The block added to the AM is a register (RE that stores the data input / output in synchronization with the SCLK signal).
G). The entire block shown in FIG. 11 constitutes one bank and belongs to either bank 1 or bank 2.

FIG. 12 is a block diagram showing one bank configuration example of the synchronous DRAM, and FIG. 13 is a block diagram showing another bank configuration example of the synchronous DRAM. As shown in FIGS. 12 and 13, banks CNTL 101 and 102 are provided to control the banks. Banks CNTL101 and 102 are respectively
The control system circuit block includes a row address buffer, a row address decoder, a sense amplifier drive system circuit, and the like. The bank is a row address in a broad sense. The bank address signal for selecting the bank is supplied to the bank CNTL101, simultaneously with other row addresses.
It is taken in by 102. Here, it is assumed that the bank 1 is selected when the bank address signal BA is at "0" level, and the bank 2 is selected when the bank address signal BA is at "1" level.

FIG. 14 is a waveform diagram of main signals of the synchronous DRAM. The standard synchronous DRAM employs the pulse RAS method. The operation regarding a plurality of banks will be described with reference to FIG.

As shown in FIG. 14, when the SCLK signal rises and the row address strobe signal (/ RAS) is at "L" level, the bank address signal BA is fetched and corresponds to the fetched bank address signal BA. The bank to be activated is activated. Here, since the bank address signal BA is at "0" level, the bank 1 is activated. When the bank 1 is activated, a word line corresponding to another row address (RAi; i = 0, 1, ..., K; k is a positive integer) fetched at the same time is selected and held in the memory cell. Data is read out to the bit line. After that, the data read to the bit line is differentially amplified by the sense amplifier. Since the word line selection and the bit line sensing operation are the same as those in the general-purpose DRAM, the description thereof will be omitted here.

Further, when the SCLK signal rises later,
If the CAS signal is at "L" level, the column address C
Since Aj has been fetched and the SCLK signal has risen after a predetermined number (called CAS latency), the data of the continuous column of the fixed number (called the burst length) of the data of the column corresponding to the column address CAj has been stored. Is output.

Regarding the operation of a plurality of row-related banks, for example, since the bank 1 is selected during the series of operations described above, the bank 2 is in the non-selected precharge state during that time. Then, when the / RAS signal becomes the "L" level next time, the bank 2 is selected.

As described above, since the synchronous DRAM apparently has no precharge time, the same number of inputs / outputs (I
The data bus width can be almost doubled as compared with the general-purpose DARM having the / O number).

Therefore, the synchronous DRAM having two banks is useful because it can have a data bus width almost double that of a general-purpose DRAM. It should be noted that a general-purpose DRAM is characterized by having a plurality of banks corresponding to row addresses even if it is not a standard synchronous DRAM.
When applied to, the data bus width can be increased.

[0022]

As described above, a memory having a plurality of banks corresponding to row addresses is effective in that the data bus width can be increased. However, it also has problems as described below.

The most power consuming operation of the DRAM is the sensing operation of the data read from the memory cell. In the case of the synchronous DRAM, only one bank is activated at the same time, but apparently the sensing operation is always performed, and therefore the power consumption accompanying the sensing operation is almost twice that of the general-purpose DRAM.

Further problems are as follows. In case of multiple bank system, the column system is common,
Each I / O requires a bus connecting bank 1 and bank 2 and a changeover switch.

Since the bank is a row address in a broad sense, each of the bank 1 and the bank 2 requires a row control circuit such as a row decoder and a sense amplifier activation circuit. The layout of the row control circuits and the layout of the data bus connecting the banks 1 and 2 are shown in FIGS. 12 and 13.

FIG. 12 shows an arrangement in which the bank 1 and the bank 2 are completely separated right and left. Since only one of the banks needs to be selected, the row control circuits can be completely separated.

However, if the row control circuit is completely separated, each I / O is also separated, so that the data bus connecting each bank becomes long, and at the center of the chip,
The bus lines for each I / O run in parallel, which is a loss in chip size.

On the other hand, as shown in FIG.
If the banks are arranged adjacent to each other for each O, the data bus connecting the bank 1 and the bank 2 can be shortened, and a large number of data buses do not run in parallel.

However, with the memory cell array of bank 1,
Since the memory cell arrays of the bank 2 are mixed, the bank 1 and the bank 2 must be driven separately, and the control method and the control pattern must be complicated.

The present invention has been made in view of the above points, and an object thereof is to reduce the data bus width while keeping the power consumption, the chip size, and the complexity associated with the arrangement of the bank control system circuit comparable to those of a general-purpose DRAM. It is an object of the present invention to provide a semiconductor memory device that can be increased in size and an operating method thereof.

[0031]

In order to achieve the above object, the present invention relates to a first aspect in which a plurality of memory cells are connected and data is exchanged with a selected cell among these memory cells. A second bank different from the first bank, in which a first local data line belonging to the bank is connected to a plurality of memory cells and data is exchanged with a selected cell among these memory cells. A second local data line belonging to, and a bank to be selected from the at least two first and second banks,
It is characterized in that it is provided with a selecting means for selecting by a control signal group including at least a column system control signal, and that the bank division is a column system instead of a row system.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION A column 2-bank DRAM according to an embodiment of the present invention will be described below. FIG. 1 is a column system 2-bank DRAM according to an embodiment of the present invention.
2A is a block diagram, and FIG. 1B is a circuit diagram.

In this description, the number of banks is set to two for easy understanding of the invention, but the number of banks may be set to two or more. . As shown in FIGS. 1A and 1B, a memory cell array 1 in which dynamic memory cells are integrated in a matrix is provided on a semiconductor chip. A row decoder (R / D) 3 for selecting a row of the memory cell array 1
Are arranged along one side of the memory cell array 1. The memory cell array 1 is added to the row decoder (R / D) 3.
A pair of global data lines (RW
D, BRWD) are arranged. Sense amplifier (S /
Regions 5-1 and 5-2 in which the A) group and the local data line pair (DQ, BDQ) group are arranged are
They are arranged along the remaining two sides. The local data line group arranged in the area 5-1 is connected to the global data line (R) via the DQ buffer group (DQB) 7-1.
WD, BRWD), while the local data line group arranged in the area 5-2 is a DQ buffer group (DQ
B) Global data line (RWD, BRW) via 7-2
D). The configuration so far is basically
This is the same as general-purpose DRAM and synchronous DRAM.

Further, in the DRAM according to the embodiment, two banks, that is, bank 1 and bank 2 are set respectively, and in order to select one of these two banks, a bank control circuit ( BD) 9 is provided. The bank control circuit (BD) 9 controls the DQ buffer groups (DQB) 7-1 and 7-2, respectively, and the bank selection is performed by the DQ buffer groups (DQB) 7-1 and 7-2. I have to. In the DRAM according to this embodiment,
DQ buffer group (DQB) 7-1 belongs to bank 1 and
The buffer group (DQB) 7-2 belongs to the bank 2. D
The Q buffer groups (DQB) 7-1 and 7-2 belonging to either bank 1 or bank 2 are selected according to the signal output from the bank control circuit (BD) 9.

Next, the operation of the DRAM according to the embodiment will be described in relation to its configuration. Since it is best to perform the interleave operation in order to make the best use of the characteristics of the DRAM according to the embodiment, the operation to be performed from now on will also be described focusing on the interleave operation.

A column address buffer system circuit, a read / write control system circuit, an input / output buffer system circuit, and the like, which are not shown, are not arranged for each bank in order not to increase the chip area unnecessarily. In a general-purpose DRAM, such a circuit group is basically activated by the fall of the / CAS signal and enters the precharge operation by the rise of the / CAS signal. However, the column-based two-bank DRA according to this embodiment
In M, the / CAS signals, that is, / CAS1 signal and / CAS2 signal are set corresponding to the two banks. The / CAS signals corresponding to each bank are / CAS1 and / CAS2 signals. These two / CAS signals, that is, the / CAS1 signal and the / CAS2 signal have a waveform such that at least one of them becomes "L" level. With such / CAS1 and / CAS2 signals,
There is no time to precharge the above circuits that are common to bank 1 and bank 2. Therefore, / CAS1 signal, / CAS
If the two signals have a skew, bank 1 and bank 2 may be activated at the same time.

In order to solve such a problem, the DRAM according to this embodiment is devised as follows. FIG. 2 is a circuit diagram of the bank control circuit.

As shown in FIG. 2, / CAS1 signal, / C
A circuit is provided that outputs an internal pulse signal BCASIN that maintains the "L" level for a certain period of time when either of the AS2 signals drops. In the general-purpose DRAM, the circuit group which was controlled by the fall and rise of the / CAS signal is controlled by the fall and rise of the internal pulse signal BCASIN.

Next, the operation of the internal pulse signal BCASIN will be described. There are three basic modes of DRAM that can be performed in one / CAS signal cycle: a read mode, a write mode, and a read modify write (abbreviated as RMW) mode. Of these three modes, only the RMW mode has a clearly longer cycle time than the other modes. Therefore, if the RMW mode is found, the internal pulse signal BCAS
The pulse width of IN is extended as needed.

FIGS. 4, 5 and 6 are waveform diagrams of main signals in the column system 2-bank DRAM according to the embodiment of the present invention. [Read Mode] First, FIG. 4 shows waveforms of main signals in the read mode.

As shown in FIG. 4, when the / RAS signal drops, the write enable signal / WE (not shown in FIG. 4,
(See Fig. 2) and output enable signal / OE
The signals are set to the “H” level.

The signal WEH (not shown in FIG. 4, see FIG. 2) is the / WE signal being "H" when the / RAS signal falls.
If it is the level, it becomes the “H” level, and when the / RAS signal falls, if the / WE signal is the “L” level, it becomes the “L”
This is a level signal.

In the read mode, the / WE signal is always at "H" level. Therefore, the node N10 shown in FIG. 2 is always at "H" level. Therefore,
The signal BCASIN is generated by the pulse generation circuit 20 or the pulse generation circuit 30 from the / CAS1 signal and the / CAS signal.
When either one of the two signals drops, it becomes an internal pulse that maintains the "L" level for a certain period. However, the delay times of the delay circuits provided in the pulse generation circuits 20 and 30 are, respectively, when the pulse width of the signal BCASIN is / CA.
The S1 signal (/ CAS2 signal) is adjusted so as not to exceed the "L" level time.

[Write Mode] FIG. 5 shows waveforms of main signals in the write mode. As shown in Fig. 5, when the / RAS signal drops, the / WE signal goes "L".
Level, and the / OE signal is set to "H" level. W
The EH signal is at "L" level. Therefore, the node N10 shown in FIG. 2 is always at "H" level. Therefore,
The signal BCASIN is generated by the pulse generation circuit 20 or 30 by the / CAS1 signal or / CAS.
When either one of the two signals drops, it becomes an internal pulse that maintains the "L" level for a certain period.

[RMW Mode] FIG. 6 shows waveforms of main signals in the RMW mode. As shown in Fig. 6, when / RAS signal drops, / WE signal and /
The OE signal is set to the "H" level. The WEH signal is at "H" level. Also, / CAS1 signal (/ C
When the AS2 signal) falls, the / WE signal is at "H" level, but after a certain period of time, it becomes "L" level. Therefore, the node N50 shown in FIG. 2 changes from the "L" level to the "H" level, so that the "L" pulse appears at the node N10. While the node N10 is at "L" level, BC
The ASIN signal is at "L" level. That is, in the RMW mode, the pulse width of the BCASIN signal is extended.
However, in order to clearly distinguish it from the read mode, / CA
A reference is required for the time difference between the S1 signal (/ CAS2 signal) and / WE falling. That is, if the / WE signal does not become "L" level within a certain period, the cycle is regarded as a read mode.

The bank is selected by the / CAS signal. That is, when the / CAS1 signal becomes "L", the bank address signal BA becomes "0" level and the bank 1 is selected.
When the / CAS2 signal becomes "L", the bank address signal BA becomes "1" level and the bank 2 is selected. A circuit for selecting such a bank is also included in the circuit shown in FIG.

FIG. 3 is a block diagram showing the flow of column addresses. As shown in FIGS. 4, 5 and 6, the column address has setup and hold times for all / CAS signal drops. Therefore, when the cycle time is short, it is necessary to fetch the column address of the next cycle while the internal column address is valid.

In order to satisfy this requirement, as shown in FIG. 3, in the DRAM according to this embodiment, an intermediate portion is provided between the column address buffer (CAB) and the column decoder or the column partial decoder. A column address latch (IAL) is provided.

7 and 8 are waveform diagrams of main signals including column-related control signals in the column-based two-bank DRAM according to the embodiment of the present invention. As shown in FIG. 3, when the signal for controlling the column address buffer (CAB) is CLTC and the signal for controlling the intermediate column address latch is ILTC, the column address operation is as shown in FIGS. 7 and 8. become.

That is, when the / CAS1 signal drops, the internal pulse signal BCASIN also drops. Internal pulse signal B
While CASIN is at "H" level, the first column address control signal CLTC (hereinafter abbreviated as "first control signal") is at "L" level. Therefore, although the column address buffer (CAB) is released, the first control signal CLTC is generated as the internal pulse signal BCASIN drops.
It goes to "L" level and the column address is latched. On the other hand, the second column address control signal ILTC (hereinafter referred to as the second column address control signal ILTC
(Abbreviated as control signal) is a pulse operation, and the first control signal C
Since the LTC becomes the “L” level for a short time while the LTC is at the “H” level, the column address latched by the first control signal CLTC at “H” is transferred to the intermediate address column latch within this short time. Transferred. Then, while the second control signal ILTC is at the “H” level, the first control signal CL is again generated.
TC becomes "L" level to prepare for the next / CAS2 signal drop. After that, these operations are repeated.

By such an operation, it is possible to solve the problem relating to the fetching of the column address, such as the problem that the banks 1 and 2 are simultaneously activated as described above.

Based on the above, the DRAM according to the embodiment of the present invention is classified into three basic modes.
This will be described in more detail. In this description, in order to make the invention easier to understand, it is assumed that the page mode is in progress, and the / CAS1 signal is at the "H" level and the / CAS2 signal is at the "L" level in the initial state.

Further, from the row address acquisition to the word line selection to the sense operation of the sense amplifier, a general purpose D is used.
Since it is similar to the case of the RAM, its description is omitted here.

[Read Mode] FIG. 4 shows time-varying waveforms of main external input signals and main internal signals.
Shows more detailed time-varying waveforms of the main external input signal and the main internal signal.

As shown in FIG. 7, the initial state is / CAS.
Since the 1 signal is at the "H" level and the / CAS2 signal is at the "L" level, bank 2 is selected. First control signal CL
TC is at “L” level, the second control signal ILTC is at “H” level, and the column selection line CSLz corresponding to the intermediate column address latch output AjCz is selected. And
The DQ buffer corresponding to bank 2 is also selected, and the data D (2
z) is appearing.

Since the / WE signal is at the "H" level when the / CAS1 signal falls, it is judged to be the read mode.
Further, as shown in FIG. 7, the internal pulse signal BCASIN becomes "L" level due to the fall of the / CAS1 signal, but in the read mode, the internal pulse signal BCASIN becomes "H" level again in the shortest time determined. Become. /
At the time of the fall of the CAS1 signal, the first control signal CLTC
Is "L", the column address CAj given from the outside is taken into the column address buffer CABj, and the first control signal CLTC after a certain delay time from the fall of the / CAS1 signal is at "H" level, Address Aj
CFa is determined. Then, the second control signal ILTC and the data line precharge signal DEQ (not shown) become "L" pulses after a certain delay time from the "H" level of the first control signal CLTC. Previous cycle address Aj
The local data line pair (DQ, BDQ), the DQ buffer, the global data line pair (RWD, BRWD) in which the data corresponding to Cz appears are precharged when the DEQ signal becomes “L” level. And
The address AjCa is transferred from the column output buffer to the intermediate column address latch. Along with this, the address Aj
The column selection line CSLa corresponding to Ca is selected, and the data of the bit line pair (BL, BBL) is read to the local data line pair (DQ, BDQ) and further to the DQ buffer. At this point, since the bank 1 has already been determined, only the DQ buffer on the bank 1 side is selected, and the final column address and the decoded data of the bank are
It is output to the global data line pair (RWD, BRWD). Since the global data line pair (RWD, BRWD) and thereafter are common to the bank 1 and the bank 2, the read data is controlled by the above-mentioned internal pulse signal BCASIN, and the read data is output via an output data line and an output buffer (not shown). , Is output to the outside of the device.

[Write Mode] FIG. 5 shows time-varying waveforms of main external input signals and main internal signals.
Shows more detailed time-varying waveforms of the main external input signal and the main internal signal.

As shown in FIG. 7, in the initial state, the / CAS1 signal is at the "H" level, / CAS, as in the read mode.
The two signals are at the “L” level, and the bank 2 is selected. The first control signal CLTC is at “L” level, the second control signal ILTC is at “H” level, and the column selection line CSLz corresponding to the intermediate column address latch output AjCFz is selected. The DQ buffer corresponding to bank 2 is also selected, and the data D (2z) of bank 2 appears on the input data bus.

Since the / WE signal is at the "L" level when the / CAS1 signal falls, it is determined to be the write mode.
Even if the / WE signal is "H" level when the / CAS1 signal drops and the / WE signal then drops to "L" level, the so-called delayed write (Del
ayeed Write) mode, but in this case,
Since the cycle time is slightly extended and there is no essential difference in explaining the operation of the DRAM according to the one embodiment, here, at the time of the / CAS1 signal falling, /
It is assumed that the WE signal is at "L" level.

Further, as shown in FIG. 7, the internal pulse signal BCASIN becomes "L" level due to the fall of the / CAS1 signal, but since it is the write mode, the internal pulse signal BCASIN is again set to "H" at the predetermined shortest time. "It becomes a level. At the time when the / CAS1 signal falls, the first control signal CLTC is "L", so that the column address CAj given from the outside corresponds to the column address buffer CAB.
The address AjCFa is fixed at the "H" level of the first control signal CLTC which is fetched by j and after a certain delay time from the fall of the / CAS1 signal. Then, the first control signal C
After the LTC has passed a certain delay time from the “H” level, the second
Control signal ILTC and data line precharge signal DE
Q (not shown) becomes an "L" pulse. The local data line pair (DQ, BDQ), the DQ buffer, the global data line pair (RWD, BRWD) in which the data corresponding to the previous cycle address AjCz appears are precharged when the DEQ signal becomes “L” level. To be done.
Then, the address AjCa is transferred from the column output buffer to the intermediate column address latch. Prior to this,
The write data is transferred from the input buffer common to the bank 1 and the bank 2 to the DQ buffer via the input data line under the control of the internal pulse signal BCASIN. Further, at this point, since the bank 1 has already been determined, only the DQ buffer on the bank 1 side is selected, and the final column address and the decoded data of the bank are the local data line pairs (DQ, BD).
Q). Therefore, the address Aj
By selecting CSLa corresponding to Ca, the data of the local data line pair (DQ, BDQ) is written to the desired bit line pair (BL, BBL).

In this way, also in the write mode, the system of two column banks operates basically in the same operation as in the read mode. [RMW Mode] FIG. 6 shows time-varying waveforms of main external input signals and main internal signals, and FIG. 8 shows more detailed time-varying waveforms of main external input signals and main internal signals. There is.

As shown in FIG. 8, in the initial state, the / CAS1 signal is at the "H" level and the / CAS2 signal is at the "L" level, as in the read mode and the write mode.
Bank 2 is selected. The first control signal CLTC is at “L” level, the second control signal ILTC is at “H” level, and the column selection line CSLz corresponding to the intermediate column address latch output AjCFz is selected. The DQ buffer corresponding to bank 2 is also selected, and the data D (2z) of bank 2 appears on the input data bus.

As described above, in the RMW mode,
The cycle time is always longer than that in the read or write mode alone. / At the time of the CAS1 signal drop
Since the / WE signal is at the "H" level, it cannot be determined whether it is the read mode or the RMW mode. However, in either mode, the read operation is required first. Therefore, when the / CAS1 signal drops, the / WE signal becomes "H".
If it is a level, the read operation is performed for the time being.

Further, as shown in FIG. 8, the internal pulse signal BCASIN becomes "L" level due to the fall of the / CAS1 signal. If the / WE signal keeps the "H" level for a certain period of time as it is, this is the read mode, so the above-mentioned read mode operation is performed. What if / C
If the / WE signal becomes "L" level within a certain time after the AS signal has fallen, it is judged to be the RMW mode, and at the time when the internal pulse signal BCASIN becomes "H" level, the / WE signal changes from "L" level. Internal pulse signal B
The time when CASIN is at the “L” level is longer than in the read mode and the write mode.

The control of the first control signal CLTC and the second control signal ILTC is the same as in the read mode and the write mode described above. At the time of the / CAS1 signal drop, the first control signal CLTC is "L", so the externally applied column address CAj is taken into the column address buffer CABj, and the / CAS1 signal drops for a certain delay time. When the subsequent first control signal CLTC is at “H” level, the address AjCFa is determined. Then, the second control signal ILTC and the data line precharge signal DEQ (not shown) become "L" pulses after a certain delay time from the "H" level of the first control signal CLTC. The local data line pair (DQ, BDQ), the DQ buffer, the global data line pair (RWD, BRWD) in which the data corresponding to the previous cycle address AjCz appears are precharged when the DEQ signal becomes “L” level. To be done. Then, the address AjCa is transferred from the column output buffer to the intermediate column address latch. Along with this, the column selection line CSLa corresponding to the column address CAja is selected, and the bit line pair (BL, BB
The data of L) is read out to the local data line pair (DQ, BDQ) and further to the DQ buffer. At this point, since the bank 1 has already been determined, only the DQ buffer on the bank 1 side is selected, and the final column address and decoded data of the bank are output to the global data line pair (RWD, BRWD). It After the global data line pair (RWD, BRWD), bank 1 and bank 2
Since it is common to the output data line, which is controlled by the internal pulse signal BCASIN and read out,
It is output via the output buffer.

In the above series of read operations, the internal pulse signal BCASIN is at the "L" level, the / WE signal is / WE,
It is completed by the time when both the IN signals become the “L” level and the write operation starts.

After this, when the write operation is started, the following operation continues. Write data is transferred by an internal pulse signal BCASIN from an input buffer (not shown) common to banks 1 and 2 to the DQ buffer via an input data line. Since the column address of the bank is the same as that of the bank during the read operation, only the DQ buffer on the bank 1 side is selected, and the final column address and the decoded data of the bank are the local data line pair (DQ, BDQ). ) Is written. Therefore, along with this, the column selection line CSL corresponding to the column address AjCa
Since a remains selected, the local data line pair (D
Q, BDQ) data is the desired bit line pair (BL, BB
L).

As described above, even in the case of the RMW mode, the CAS
Cycle time and internal pulse signal BCASIN are "L"
Basically, the column 2-bank system operates basically in the same manner as in the read mode and the write mode, only by increasing the level time.

The column system 2 according to such an embodiment
The bank semiconductor memory device has the following advantages over the conventional row-type two-bank semiconductor memory device.
First, the first advantage is that the row system can be activated only once per / RAS signal cycle, so that the power consumption due to the sense amplifier operation, which accounts for a significant portion of the power consumption of DRAM, is almost the same as that of general-purpose DRAM. The same thing can be done equivalently.

The second advantage is the column system 2 according to the present invention.
In the bank DRAM, it is possible to hardly change the configuration of the core portion of the general-purpose DRAM. That is, as described above, in the recent DRAM in which the sense amplifiers are arranged on the left and right of the memory cell array, the local data line pair (D
Q, BDQ) and DQ buffers also need to be arranged corresponding to the sense amplifiers.

Further, in order to perform the final decoding of the column address in the DQ buffer, the data of the bit line is read out to the local data line pair (DQ, BDQ) and the DQ buffer. Therefore, in the general-purpose DRAM, it is the column address that selects two DQ buffers. In the column 2-bank DRAM of the present invention, however, the two DQ buffers have data latches and banks corresponding to bank 1 and bank 2, respectively. It only needs to have the function of a changeover switch. As described above, the column-based 2-bank DRAM according to the present invention can be achieved without substantially changing the configuration of the core portion of the general-purpose DRAM.

The third advantage is FP (first page)
This means that it is easy to use the mode and EDO (Extended Data Out) mode together. Since there are two / CAS signals and each controls each bank, data can be output for each bank. Especially two / CAS
In the case of so-called interleaved operation in which signals are applied in opposite phases, a data bus width almost double that in the page mode of a general-purpose DRAM can be achieved.

[0073]

As described above, according to the present invention, a semiconductor memory device capable of increasing the data bus width while keeping the power consumption, the chip size, and the complexity associated with the arrangement of the bank control system circuit on par with a general-purpose DRAM. And a method of operating the same can be provided.

[Brief description of the drawings]

1A and 1B are diagrams showing a core of a column system 2-bank DRAM according to an embodiment of the present invention, FIG. 1A is a block diagram, and FIG. 1B is a circuit diagram.

FIG. 2 is a circuit diagram of a bank control circuit.

FIG. 3 is a block diagram showing the flow of column addresses.

FIG. 4 is a signal waveform diagram showing input / output waveforms in the read mode of the column system 2-bank DRAM according to the embodiment of the present invention.

FIG. 5 is a signal waveform diagram showing an input waveform in the write mode of the column system 2-bank DRAM according to the embodiment of the present invention.

FIG. 6 is a signal waveform diagram showing input / output waveforms in the RMW mode of the column 2-bank DRAM according to the embodiment of the present invention.

FIG. 7 is a signal waveform diagram showing column address system control signals and time change waveforms of data in a read / write mode of a column system two bank DRAM according to an embodiment of the present invention.

FIG. 8 is a signal waveform diagram showing a time change waveform of a column address system control signal and data in a RMW mode of a column system 2-bank DRAM according to an embodiment of the present invention.

FIG. 9 is a signal waveform diagram showing input / output waveforms in a first page mode and an extended data out mode.

10A and 10B are diagrams showing a core of a conventional general-purpose DRAM, wherein FIG. 10A is a block diagram and FIG. 10B is a circuit diagram.

FIG. 11 is a block diagram showing a core of a general synchronous DRAM.

FIG. 12 is a row-related two-bank synchronous DR.
The block diagram which shows an example of AM.

FIG. 13 is a row 2 bank synchronous DR.
The block diagram which shows the other example of AM.

FIG. 14 is a signal waveform diagram showing typical input / output waveforms of a synchronous DRAM.

[Explanation of symbols]

1 ... Memory cell array, 3 ... Row decoder, 5-1 and 5-2
... areas where local data line pairs are located, 7-1, 7-2 ...
Local data line buffer, 9 ... Bank control circuit.

Claims (10)

[Claims] 1. A first local data line belonging to a first bank, to which a plurality of memory cells are connected, and data is exchanged with a selected cell among these memory cells, and a plurality of memory cells. And a second local data line belonging to a second bank different from the first bank for exchanging data with a selected cell among these memory cells, and the at least two second data lines. From the 1st and 2nd banks,
A semiconductor memory device comprising: a selecting unit that selects a bank to be selected by a control signal group including at least a column control signal. 2. The control signal group includes first and second column system control signals that interleave with each other,
2. The semiconductor memory device according to claim 1, wherein data is read from the memory cell to the outside or data is written to the memory cell from the outside according to the first and second column system control signals. 3. A pulse which holds a certain signal level for a predetermined time in accordance with a signal level change of one of the first and second column system control signals interleaving with each other in the selecting means. 3. The semiconductor memory device according to claim 2, further comprising an internal control signal generation circuit that outputs a uniform internal control signal. 4. The semiconductor memory device according to claim 3, wherein the internal control signal generation circuit changes the pulse width of the internal control signal according to an operation mode of the semiconductor memory device. 5. A first and second local data line to which a plurality of memory cells are connected, and a global data line commonly connected to the first and second local data lines, The first and second local data lines are respectively
A semiconductor memory device characterized by being divided into a second bank. 6. The data from the first local data line and the data from the second local data line are interleaved with each other by interleaving the first local data line and the second local data line. Alternately output to the global data line to perform a data read operation,
6. The semiconductor memory device according to claim 5, wherein the data write operation is performed by alternately inputting data from the global data line to the first local data line and the second local data line. . 7. In addition to the read operation and the write operation, a data read operation for outputting one of the first and second local data lines to the global data line and a data read operation for the global data line are performed. A read-modify-write operation that sequentially performs a write operation of data input to either the first or second local data line is alternately performed in the first bank and the second bank. 7. The semiconductor memory device according to claim 5 or claim 7. 8. The first local data line buffer provided between the first local data line and the global data line, and between the second local data line and the global data line. 7. A second local data line buffer provided, wherein the selection of the first and second banks is performed by the first and second local data line buffers. The semiconductor memory device according to claim 7. 9. The first local data line is arranged along one side of a memory cell in which the memory cell is integrated, and the second local data line is formed by integrating the memory cell. 9. The semiconductor memory device according to claim 8, wherein the semiconductor memory device is arranged along the other side of the existing memory cell. 10. A first memory cell comprising a plurality of memory cells connected to each other,
A method of operating a semiconductor memory device, comprising: a second local data line; and a global data line commonly connected to the first and second local data lines. A method of operating a semiconductor memory device, characterized in that the lines are divided into first and second banks, respectively, and the first and second banks are alternately activated.