DE60106011D1 - Verfahren zur Bildung einer Isolierschicht und Verfahren zur Herstellung eines Grabenkondensators - Google Patents

Verfahren zur Bildung einer Isolierschicht und Verfahren zur Herstellung eines Grabenkondensators

Info

Publication number
DE60106011D1
DE60106011D1 DE60106011T DE60106011T DE60106011D1 DE 60106011 D1 DE60106011 D1 DE 60106011D1 DE 60106011 T DE60106011 T DE 60106011T DE 60106011 T DE60106011 T DE 60106011T DE 60106011 D1 DE60106011 D1 DE 60106011D1
Authority
DE
Germany
Prior art keywords
producing
forming
insulating layer
trench capacitor
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60106011T
Other languages
English (en)
Other versions
DE60106011T2 (de
Inventor
Torsten Schneider
Bruno Spuler
Christian Drabe
Jana Haensel
Anke Krasemann
Barbara Lorenz
Dr Morgenstern
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60106011D1 publication Critical patent/DE60106011D1/de
Publication of DE60106011T2 publication Critical patent/DE60106011T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
DE60106011T 2001-07-23 2001-07-23 Verfahren zur Bildung einer Isolierschicht und Verfahren zur Herstellung eines Grabenkondensators Expired - Fee Related DE60106011T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01117854A EP1282159B1 (de) 2001-07-23 2001-07-23 Verfahren zur Bildung einer Isolierschicht und Verfahren zur Herstellung eines Grabenkondensators

Publications (2)

Publication Number Publication Date
DE60106011D1 true DE60106011D1 (de) 2004-11-04
DE60106011T2 DE60106011T2 (de) 2006-03-02

Family

ID=8178121

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60106011T Expired - Fee Related DE60106011T2 (de) 2001-07-23 2001-07-23 Verfahren zur Bildung einer Isolierschicht und Verfahren zur Herstellung eines Grabenkondensators

Country Status (4)

Country Link
US (1) US6984556B2 (de)
EP (1) EP1282159B1 (de)
DE (1) DE60106011T2 (de)
WO (1) WO2003010810A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4629421B2 (ja) * 2004-12-06 2011-02-09 パナソニック株式会社 ドライエッチング方法及びドライエッチング装置
US7517804B2 (en) 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US8624312B2 (en) 2011-04-28 2014-01-07 Freescale Semiconductor, Inc. Semiconductor device structure as a capacitor
US8318577B2 (en) * 2011-04-28 2012-11-27 Freescale Semiconductor, Inc. Method of making a semiconductor device as a capacitor
US9550669B2 (en) * 2012-02-08 2017-01-24 Infineon Technologies Ag Vertical pressure sensitive structure

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62142326A (ja) * 1985-12-17 1987-06-25 Matsushita Electronics Corp エツチング方法
US6171974B1 (en) 1991-06-27 2001-01-09 Applied Materials, Inc. High selectivity oxide etch process for integrated circuit structures
JP2997142B2 (ja) * 1992-01-24 2000-01-11 アプライド マテリアルズ インコーポレイテッド 集積回路構造の選択性の高い酸化物エッチングプロセス
US5930585A (en) 1996-07-23 1999-07-27 International Business Machines Corporation Collar etch method to improve polysilicon strap integrity in DRAM chips
EP0821409A3 (de) * 1996-07-23 2004-09-08 International Business Machines Corporation Ätzverfahren für Isolationsring einer DRAM-Zelle
US6066566A (en) 1998-01-28 2000-05-23 International Business Machines Corporation High selectivity collar oxide etch processes
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
WO2002095800A2 (en) * 2001-05-22 2002-11-28 Reflectivity, Inc. A method for making a micromechanical device by removing a sacrificial layer with multiple sequential etchants
US6685803B2 (en) * 2001-06-22 2004-02-03 Applied Materials, Inc. Plasma treatment of processing gases

Also Published As

Publication number Publication date
DE60106011T2 (de) 2006-03-02
EP1282159B1 (de) 2004-09-29
US20040198015A1 (en) 2004-10-07
EP1282159A1 (de) 2003-02-05
WO2003010810A1 (en) 2003-02-06
US6984556B2 (en) 2006-01-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee